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VBAR_EL3: Vector Base Address Register (EL3)

Purpose

Holds the vector base address for any exception that is taken to EL3.

Configuration

This register is present only when EL3 is implemented. Otherwise, direct accesses to VBAR_EL3 are UNDEFINED.

Attributes

VBAR_EL3 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Vector Base Address
Vector Base AddressRES0

Bits [63:11]

Vector Base Address. Base address of the exception vectors for exceptions taken to EL3.

Note

If the implementation supports FEAT_LVA3, then:

Otherwise:

If the implementation supports FEAT_LVA, then:

If the implementation does not support FEAT_LVA, then:

The reset behavior of this field is:

Bits [10:0]

Reserved, RES0.

Accessing VBAR_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, VBAR_EL3

op0op1CRnCRmop2
0b110b1100b11000b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = VBAR_EL3;

MSR VBAR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b11000b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3.VBAR_EL3 == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else VBAR_EL3 = X[t, 64];