Returns the tracing capabilities of the trace unit.
AArch64 System register TRCIDR5 bits [31:0] are architecturally mapped to External register TRCIDR5[31:0].
This register is present only when FEAT_ETE is implemented and System register access to the trace unit registers is implemented. Otherwise, direct accesses to TRCIDR5 are UNDEFINED.
TRCIDR5 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| OE | NUMCNTR | NUMSEQSTATE | RES0 | LPOVERRIDE | ATBTRIG | TRACEIDSIZE | RES0 | NUMEXTINSEL | NUMEXTIN | ||||||||||||||||||||||
Reserved, RES0.
Indicates support for the ETE Trace Output Enable.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| OE | Meaning |
|---|---|
| 0b0 |
ETE Trace Output Enable is not implemented. |
| 0b1 |
ETE Trace Output Enable is implemented. |
When FEAT_ETEv1p3 is implemented and when any IMPLEMENTATION DEFINED trace output interface is implemented, this field is 1.
Access to this field is RO.
Indicates the number of Counters that are available for tracing.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NUMCNTR | Meaning |
|---|---|
| 0b000..0b100 |
The number of Counters implemented. |
All other values are reserved.
If TRCIDR4.NUMRSPAIR == 0b0000 then this field is 0b000.
Access to this field is RO.
Indicates if the Sequencer is implemented and the number of Sequencer states that are implemented.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NUMSEQSTATE | Meaning |
|---|---|
| 0b000 |
The Sequencer is not implemented. |
| 0b100 |
Four Sequencer states are implemented. |
All other values are reserved.
If TRCIDR4.NUMRSPAIR == 0b0000 then this field is 0b000.
Access to this field is RO.
Reserved, RES0.
Indicates support for Low-power Override Mode.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| LPOVERRIDE | Meaning |
|---|---|
| 0b0 |
The trace unit does not support Low-power Override Mode. |
| 0b1 |
The trace unit supports Low-power Override Mode. |
Access to this field is RO.
Indicates if the implementation can support ATB triggers.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| ATBTRIG | Meaning |
|---|---|
| 0b0 |
The implementation does not support ATB triggers. |
| 0b1 |
The implementation supports ATB triggers. |
If TRCIDR4.NUMRSPAIR == 0b0000 then this field is 0.
Access to this field is RO.
Indicates the trace ID width.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| TRACEIDSIZE | Meaning |
|---|---|
| 0b000000 |
The external trace interface is not implemented. |
| 0b000111 |
The implementation supports a 7-bit trace ID. |
All other values are reserved.
AMBA ATB requires a 7-bit trace ID width.
Access to this field is RO.
Reserved, RES0.
Indicates how many External Input Selector resources are implemented.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NUMEXTINSEL | Meaning |
|---|---|
| 0b000..0b100 |
The number of External Input Selector resources implemented. |
All other values are reserved.
Access to this field is RO.
Indicates how many External Inputs are implemented.
| NUMEXTIN | Meaning |
|---|---|
| 0b111111111 |
Unified PMU event selection. |
All other values are reserved.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, TRCIDR5
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b001 | 0b0000 | 0b1101 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRCID == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRCIDR5; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRCIDR5; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELUsingAArch32(EL1) && IsFeatureImplemented(FEAT_TRBE_EXT) && OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR2.TTA == '1' then Halt(DebugHalt_SoftwareAccess); else X[t, 64] = TRCIDR5;