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TPIDRRO_EL0: EL0 Read-Only Software Thread ID Register

Purpose

Provides a location where software executing at EL1 or higher can store thread identifying information that is visible to software executing at EL0, for OS management purposes.

The PE makes no use of this register.

Configuration

AArch64 System register TPIDRRO_EL0 bits [31:0] are architecturally mapped to AArch32 System register TPIDRURO[31:0].

Attributes

TPIDRRO_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Thread ID
Thread ID

Bits [63:0]

Thread ID. Thread identifying information stored by software running at this Exception level.

Accessing TPIDRRO_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TPIDRRO_EL0

op0op1CRnCRmop2
0b110b0110b11010b00000b011

if PSTATE.EL == EL0 then if EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TPIDRRO_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = TPIDRRO_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TPIDRRO_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = TPIDRRO_EL0; elsif PSTATE.EL == EL2 then X[t, 64] = TPIDRRO_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = TPIDRRO_EL0;

MSR TPIDRRO_EL0, <Xt>

op0op1CRnCRmop2
0b110b0110b11010b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TPIDRRO_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TPIDRRO_EL0 = X[t, 64]; elsif PSTATE.EL == EL2 then TPIDRRO_EL0 = X[t, 64]; elsif PSTATE.EL == EL3 then TPIDRRO_EL0 = X[t, 64];