If EL2 is implemented and enabled in the current Security state, invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
The entry is one of the following:
A 64-bit stage 2 only translation table entry, from any level of the translation table walk.
If FEAT_D128 is implemented, a 128-bit stage 2 only translation table entry, from any level of the translation table walk, if TTL[3:2] is 0b00.
If FEAT_RME is implemented, one of the following applies:
If FEAT_RME is not implemented, one of the following applies:
The entry would be used with the current VMID.
The invalidation is not required to apply to caching structures that combine stage 1 and stage 2 translation table entries.
The invalidation applies to the PE that executes this System instruction.
For more information about the architectural requirements for this System instruction, see 'Invalidation of TLB entries from stage 2 translations'.
If FEAT_XS is implemented, the nXS variant of this System instruction is defined.
Both variants perform the same invalidation, but the TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.
The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.
There are no configuration notes.
TLBI IPAS2E1, TLBI IPAS2E1NXS is a 64-bit System instruction.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NS | RES0 | TTL | IPA[55:52] | IPA[51:48] | IPA[47:12] | ||||||||||||||||||||||||||
| IPA[47:12] | |||||||||||||||||||||||||||||||
When the instruction is executed and SCR_EL3.{NSE, NS} == {0, 0}, NS selects the IPA space.
| NS | Meaning |
|---|---|
| 0b0 |
IPA is in the Secure IPA space. |
| 0b1 |
IPA is in the Non-secure IPA space. |
When the instruction is executed and SCR_EL3.{NSE, NS} == {1, 1}, this field is RES0, and the instruction applies only to the Realm IPA space.
When the instruction is executed and SCR_EL3.{NSE, NS} == {0, 1}, this field is RES0, and the instruction applies only to the Non-secure IPA space.
Not Secure. Specifies the IPA space.
| NS | Meaning |
|---|---|
| 0b0 |
IPA is in the Secure IPA space. |
| 0b1 |
IPA is in the Non-secure IPA space. |
When the instruction is executed in Non-secure state, this field is RES0, and the instruction applies only to the Non-secure IPA space.
When FEAT_SEL2 is not implemented, or if EL2 is disabled in the current Security state, this field is RES0.
Reserved, RES0.
Reserved, RES0.
Translation Table Level. Indicates the level of the translation table walk that holds the leaf entry for the address being invalidated.
| TTL | Meaning |
|---|---|
| 0b00xx |
No information supplied as to the translation table level. Hardware must assume that the entry can be from any level. In this case, TTL<1:0> is RES0. |
| 0b01xx | The entry comes from a 4KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : If FEAT_LPA2 is implemented, level 0. Otherwise, treat as if TTL<3:2> is 0b00. 0b01 : Level 1. 0b10 : Level 2. 0b11 : Level 3. |
| 0b10xx | The entry comes from a 16KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : Reserved. Treat as if TTL<3:2> is 0b00. 0b01 : If FEAT_LPA2 is implemented, level 1. Otherwise, treat as if TTL<3:2> is 0b00. 0b10 : Level 2. 0b11 : Level 3. |
| 0b11xx | The entry comes from a 64KB translation granule. The level of walk for the leaf level 0bxx is encoded as: 0b00 : Reserved. Treat as if TTL<3:2> is 0b00. 0b01 : Level 1. 0b10 : Level 2. 0b11 : Level 3. |
If an incorrect value of the TTL field is specified for the entry being invalidated by the instruction, then no entries are required by the architecture to be invalidated from the TLB.
Reserved, RES0.
Extension to IPA[47:12]. For more information, see IPA[47:12].
Reserved, RES0.
Extension to IPA[47:12]. For more information, see IPA[47:12].
Reserved, RES0.
Bits[47:12] of the intermediate physical address to match. For implementations with fewer than 48 bits, the upper bits of this field are RES0.
If ID_AA64MMFR0_EL1.PARange is 0b0111, bits IPA[55:48] form the upper part of the address value.
If ID_AA64MMFR0_EL1.PARange is 0b0110, bits IPA[51:48] form the upper part of the address value and bits IPA[55:52] are RES0.
If ID_AA64MMFR0_EL1.PARange is not 0b0110 and not 0b0111, bits IPA[55:48] are RES0.
Accesses to this instruction use the following encodings in the System instruction encoding space:
TLBI IPAS2E1{, <Xt>}
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b100 | 0b1000 | 0b0100 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then AArch64.TLBI_IPAS2(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_NSH, TLBILevel_Any, TLBI_AllAttr, X[t, 64]); elsif PSTATE.EL == EL3 then if !EL2Enabled() then return; else if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64.TLBI_IPAS2(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_NSH, TLBILevel_Any, TLBI_AllAttr, X[t, 64]);
TLBI IPAS2E1NXS{, <Xt>}
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b100 | 0b1001 | 0b0100 | 0b001 |
if !IsFeatureImplemented(FEAT_XS) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then AArch64.TLBI_IPAS2(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_NSH, TLBILevel_Any, TLBI_ExcludeXS, X[t, 64]); elsif PSTATE.EL == EL3 then if !EL2Enabled() then return; else if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64.TLBI_IPAS2(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Shareability_NSH, TLBILevel_Any, TLBI_ExcludeXS, X[t, 64]);