This register controls aspects of Streaming SVE that are visible at all Exception levels.
This register is present only when FEAT_SME is implemented and EL3 is implemented. Otherwise, direct accesses to SMCR_EL3 are UNDEFINED.
This register has no effect if the PE is not in Streaming SVE mode.
SMCR_EL3 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| FA64 | EZT0 | RES0 | RAZ/WI | LEN | |||||||||||||||||||||||||||
Reserved, RES0.
Controls whether execution of an A64 instruction is considered legal when the PE is in Streaming SVE mode.
| FA64 | Meaning |
|---|---|
| 0b0 |
This control does not cause any instruction to be treated as legal in Streaming SVE mode. |
| 0b1 |
This control causes all implemented A64 instructions to be treated as legal in Streaming SVE mode at EL3. |
Arm recommends that portable SME software should not rely on this optional feature, and that operating systems should provide a means to test for compliance with this recommendation.
The reset behavior of this field is:
Reserved, RES0.
Traps execution at all Exception levels of the LDR, LUTI2, LUTI4, MOVT, STR, and ZERO instructions that access the ZT0 register to EL3.
The exception is reported using ESR_EL3.EC value 0x1D, with an ISS code of 0x0000004, at a lower priority than a trap due to PSTATE.SM or PSTATE.ZA.
| EZT0 | Meaning |
|---|---|
| 0b0 |
This control causes execution of these instructions at all Exception levels to be trapped. |
| 0b1 |
This control does not cause execution of any instruction to be trapped. |
Changes to this field only affect whether instructions that access ZT0 are trapped. They do not affect the contents of ZT0, which remain valid so long as PSTATE.ZA is 1.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Reserved, RAZ/WI.
Requests an Effective Streaming SVE vector length (SVL) at EL3 of (LEN+1)*128 bits.
The Streaming SVE vector length can be any power of two from 128 bits to 2048 bits inclusive. An implementation can support any subset of the architecturally permitted lengths.
When the PE is in Streaming SVE mode, the Effective SVE vector length (VL) is equal to SVL.
When FEAT_SVE is implemented, and the PE is not in Streaming SVE mode, VL is equal to the Effective Non-streaming SVE vector length. See ZCR_EL3.
For all purposes other than returning the result of a direct read of SMCR_EL3, the PE selects the Effective Streaming SVE vector length by performing checks in the following order:
If the requested length is less than the minimum implemented Streaming SVE vector length, then the Effective length is the minimum implemented Streaming SVE vector length.
Otherwise, the Effective length is the highest supported Streaming SVE vector length that is less than or equal to the requested length.
An indirect read of SMCR_EL3.LEN appears to occur in program order relative to a direct write of the same register, without the need for explicit synchronization.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, SMCR_EL3
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b110 | 0b0001 | 0b0010 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else X[t, 64] = SMCR_EL3;
MSR SMCR_EL3, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b110 | 0b0001 | 0b0010 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else SMCR_EL3 = X[t, 64];