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SCTLR2_EL3: System Control Register (EL3)

Purpose

Provides top level control of the system, including its memory system, at EL3.

Configuration

This register is present only when FEAT_SCTLR2 is implemented. Otherwise, direct accesses to SCTLR2_EL3 are UNDEFINED.

Attributes

SCTLR2_EL3 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0CPTMRES0CPTARES0EnPACMRES0EnANERREnADERRRES0EMECRES0

Bits [63:12]

Reserved, RES0.

CPTM, bit [11]

When FEAT_CPA2 is implemented:

This field controls Checked Pointer Arithmetic for Multiplication at EL3.

CPTMMeaning
0b0

Pointer Arithmetic for Multiplication is not checked.

0b1

Pointer Arithmetic for Multiplication is checked.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

Bit [10]

Reserved, RES0.

CPTA, bit [9]

When FEAT_CPA2 is implemented:

This field controls Checked Pointer Arithmetic for Addition at EL3.

CPTAMeaning
0b0

Pointer Arithmetic for Addition is not checked.

0b1

Pointer Arithmetic for Addition is checked.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

Bit [8]

Reserved, RES0.

EnPACM, bit [7]

When FEAT_PAuth_LR is implemented:

PACM Enable at EL3. Controls the effect of a PACM instruction at EL3.

EnPACMMeaning
0b0

The effects of PACM are disabled at EL3.

0b1

A PACM instruction at EL3 causes PSTATE.PACM to be set to 0b1.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

Bits [6:5]

Reserved, RES0.

EnANERR, bit [4]

When FEAT_ANERR is implemented:

Enable Asynchronous Normal Read Error.

EnANERRMeaning
0b0

External aborts on Normal memory reads generate synchronous Data Abort exceptions in the EL3 translation regime.

0b1

External aborts on Normal memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL3 translation regime.

It is implementation-specific whether this field applies to memory reads generated by each of the following:

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Normal memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

Setting this field to 0 might have a performance impact for Normal memory reads.

This field is ignored by the PE and treated as one when all of the following are true:

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

EnADERR, bit [3]

When FEAT_ADERR is implemented:

Enable Asynchronous Device Read Error.

EnADERRMeaning
0b0

External aborts on Device memory reads generate synchronous Data Abort exceptions in the EL3 translation regime.

0b1

External aborts on Device memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL3 translation regime.

It is implementation-specific whether this field applies to memory reads generated by each of the following:

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Device memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

Setting this field to 0 might have a performance impact for Device memory reads.

This field is ignored by the PE and treated as one when all of the following are true:

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

Bit [2]

Reserved, RES0.

EMEC, bit [1]

When FEAT_MEC is implemented:

Enables MEC. When enabled, memory accesses to the Realm physical address space are associated with MECID_RL_A_EL3.

EMECMeaning
0b0

MEC is not enabled for the Realm physical address space.

0b1

MEC is enabled for the Realm physical address space.

This bit is permitted to be cached in a TLB.

The reset behavior of this field is:



Otherwise:

Reserved, RES0.

Bit [0]

Reserved, RES0.

Accessing SCTLR2_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SCTLR2_EL3

op0op1CRnCRmop2
0b110b1100b00010b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = SCTLR2_EL3;

MSR SCTLR2_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b00010b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3.SCTLR2_EL3 == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else SCTLR2_EL3 = X[t, 64];