SCTLR2_EL1 | Jon's Arm Reference

Provides top level control of the system, including its memory system, at EL1 and EL0.

Configuration

This register is present only when FEAT_SCTLR2 is implemented. Otherwise, direct accesses to SCTLR2_EL1 are UNDEFINED.

Attributes

Field descriptions

Bits [63:13]

CPTM0, bit [12]

When FEAT_CPA2 is implemented and the Effective value of HCR_EL2.E2H is 1:

This field controls unprivileged Checked Pointer Arithmetic for Multiplication.

CPTM0	Meaning
0b0	Pointer Arithmetic for Multiplication is not checked.
0b1	Pointer Arithmetic for Multiplication is checked.

When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution.

This field is ignored by the PE and treated as zero when any of the following are true:

EL3 is implemented and SCR_EL3.SCTLR2En == 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.SCTLR2En is 0.

If the Effective value of SCTLR2_EL1.CPTA0 is 0, then the Effective value of this field is 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

CPTM, bit [11]

When FEAT_CPA2 is implemented:

This field controls Checked Pointer Arithmetic for Multiplication at EL1.

CPTM	Meaning
0b0	Pointer Arithmetic for Multiplication is not checked.
0b1	Pointer Arithmetic for Multiplication is checked.

This field is ignored by the PE and treated as zero when any of the following are true:

EL3 is implemented and SCR_EL3.SCTLR2En == 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.SCTLR2En is 0.

If the Effective value of SCTLR2_EL1.CPTA is 0, then the Effective value of this field is 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

CPTA0, bit [10]

When FEAT_CPA2 is implemented and the Effective value of HCR_EL2.E2H is 1:

This field controls unprivileged Checked Pointer Arithmetic for Addition.

CPTA0	Meaning
0b0	Pointer Arithmetic for Addition is not checked.
0b1	Pointer Arithmetic for Addition is checked.

When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution.

This field is ignored by the PE and treated as zero when any of the following are true:

EL3 is implemented and SCR_EL3.SCTLR2En == 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.SCTLR2En is 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

CPTA, bit [9]

When FEAT_CPA2 is implemented:

This field controls Checked Pointer Arithmetic for Addition at EL1.

CPTA	Meaning
0b0	Pointer Arithmetic for Addition is not checked.
0b1	Pointer Arithmetic for Addition is checked.

This field is ignored by the PE and treated as zero when any of the following are true:

EL3 is implemented and SCR_EL3.SCTLR2En == 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.SCTLR2En is 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

EnPACM0, bit [8]

When FEAT_PAuth_LR is implemented:

PACM Enable at EL0. Controls the effect of a PACM instruction at EL0.

EnPACM0	Meaning
0b0	The effects of PACM are disabled at EL0.
0b1	A PACM instruction at EL0 causes PSTATE.PACM to be set to 0b1.

When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.

This field is ignored by the PE and treated as zero when any of the following are true:

EL3 is implemented and SCR_EL3.SCTLR2En == 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.SCTLR2En is 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.PACMEn == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

EnPACM, bit [7]

When FEAT_PAuth_LR is implemented:

PACM Enable at EL1. Controls the effect of a PACM instruction at EL1.

EnPACM	Meaning
0b0	The effects of PACM are disabled at EL1.
0b1	A PACM instruction at EL1 causes PSTATE.PACM to be set to 0b1.

This field is ignored by the PE and treated as zero when any of the following are true:

EL3 is implemented and SCR_EL3.SCTLR2En == 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.SCTLR2En is 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.PACMEn == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

EnIDCP128, bit [6]

When FEAT_SYSREG128 is implemented:

Enables access to IMPLEMENTATION DEFINED 128-bit System registers.

EnIDCP128	Meaning
0b0	Accesses at EL0 to IMPLEMENTATION DEFINED 128-bit System registers are trapped to EL1 using an ESR_EL1.EC value of 0x14, unless the access generates a higher priority exception. Disables the functionality of the 128-bit IMPLEMENTATION DEFINED System registers that are accessible at EL1.
0b1	No accesses are trapped by this control.

EnIDCP128

Meaning

0b0

Accesses at EL0 to IMPLEMENTATION DEFINED 128-bit System registers are trapped to EL1 using an ESR_EL1.EC value of 0x14, unless the access generates a higher priority exception.

Disables the functionality of the 128-bit IMPLEMENTATION DEFINED System registers that are accessible at EL1.

0b1

No accesses are trapped by this control.

This field is ignored by the PE and treated as zero when any of the following are true:

EL3 is implemented and SCR_EL3.SCTLR2En == 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.SCTLR2En is 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

EASE, bit [5]

When FEAT_DoubleFault2 is implemented:

External Aborts to SError exception vector.

EASE	Meaning
0b0	Synchronous External abort exceptions taken to EL1 are taken to the appropriate synchronous exception vector offset from VBAR_EL1.
0b1	Synchronous External abort exceptions taken to EL1 are taken to the appropriate SError exception vector offset from VBAR_EL1.

This field is ignored by the PE and treated as zero when any of the following are true:

EL3 is implemented and SCR_EL3.SCTLR2En == 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.SCTLR2En is 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

EnANERR, bit [4]

When FEAT_ANERR is implemented:

Enable Asynchronous Normal Read Error.

EnANERR	Meaning
0b0	External aborts on Normal memory reads generate synchronous Data Abort exceptions in the EL1&0 translation regime.
0b1	External aborts on Normal memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL1&0 translation regime.

It is implementation-specific whether this field applies to memory reads generated by each of the following:

SVE register loads, when FEAT_SME is implemented and the PE is in Streaming SVE mode.
SME register loads.
LD<op>, SWP and CAS{P} Atomic instructions that return a value to the PE.
LD64B and ST64BV{0} instructions that return a value to the PE.
RCW instructions that return a value to the PE.

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Normal memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

Setting this field to 0 might have a performance impact for Normal memory reads.

This field is ignored by the PE and treated as zero when any of the following are true:

EL3 is implemented and SCR_EL3.SCTLR2En == 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.SCTLR2En is 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.EnSNERR is 1.

This field is ignored by the PE and treated as one when all of the following are true:

FEAT_ADERR is implemented.
ID_AA64MMFR3_EL1.ANERR reads as 0b0010.
SCTLR2_EL1.EnADERR is 1.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

EnADERR, bit [3]

When FEAT_ADERR is implemented:

Enable Asynchronous Device Read Error.

EnADERR	Meaning
0b0	External aborts on Device memory reads generate synchronous Data Abort exceptions in the EL1&0 translation regime.
0b1	External aborts on Device memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL1&0 translation regime.

It is implementation-specific whether this field applies to memory reads generated by each of the following:

SIMD&FP register loads.
SVE register loads.
SME register loads.
LD<op>, SWP and CAS{P} Atomic instructions that return a value to the PE.
LD64B and ST64BV{0} instructions that return a value to the PE.
RCW instructions that return a value to the PE.

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Device memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

Setting this field to 0 might have a performance impact for Device memory reads.

This field is ignored by the PE and treated as zero when any of the following are true:

EL3 is implemented and SCR_EL3.SCTLR2En == 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.SCTLR2En is 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.EnSDERR is 1.

This field is ignored by the PE and treated as one when all of the following are true:

FEAT_ANERR is implemented.
ID_AA64MMFR3_EL1.ADERR reads as 0b0010.
SCTLR2_EL1.EnANERR is 1.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

NMEA, bit [2]

When FEAT_DoubleFault2 is implemented:

Non-maskable External Aborts. Controls whether PSTATE.A masks SError exceptions at EL1.

NMEA	Meaning
0b0	SError exceptions are not taken at EL1 if PSTATE.A == 1, unless routed to a higher Exception level.
0b1	SError exceptions are taken at EL1 regardless of the value of PSTATE.A, unless routed to a higher Exception level.

This field is ignored by the PE and treated as zero when any of the following are true:

EL3 is implemented and SCR_EL3.SCTLR2En == 0.
EL2 is implemented and enabled in the current Security state and the Effective value of HCRX_EL2.SCTLR2En is 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [1:0]

Accessing SCTLR2_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SCTLR2_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.SCTLR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SCTLR2En == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() == '111' then X[t, 64] = NVMem[0x278]; else X[t, 64] = SCTLR2_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = SCTLR2_EL2; else X[t, 64] = SCTLR2_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = SCTLR2_EL1;

MSR SCTLR2_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.SCTLR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SCTLR2En == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() == '111' then NVMem[0x278] = X[t, 64]; else SCTLR2_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then SCTLR2_EL2 = X[t, 64]; else SCTLR2_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then SCTLR2_EL1 = X[t, 64];

MRS <Xt>, SCTLR2_EL12

op0	op1	CRn	CRm	op2
0b11	0b101	0b0001	0b0000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X[t, 64] = NVMem[0x278]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = SCTLR2_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X[t, 64] = SCTLR2_EL1; else UNDEFINED;

MSR SCTLR2_EL12, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b101	0b0001	0b0000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem[0x278] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else SCTLR2_EL1 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then SCTLR2_EL1 = X[t, 64]; else UNDEFINED;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																			CPTM0	CPTM	CPTA0	CPTA	EnPACM0	EnPACM	EnIDCP128	EASE	EnANERR	EnADERR	NMEA	RES0

SCTLR2_EL1: System Control Register (EL1)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:13]

CPTM0, bit [12]

When FEAT_CPA2 is implemented and the Effective value of HCR_EL2.E2H is 1:

Otherwise:

CPTM, bit [11]

When FEAT_CPA2 is implemented:

Otherwise:

CPTA0, bit [10]

When FEAT_CPA2 is implemented and the Effective value of HCR_EL2.E2H is 1:

Otherwise:

CPTA, bit [9]

When FEAT_CPA2 is implemented:

Otherwise:

EnPACM0, bit [8]

When FEAT_PAuth_LR is implemented:

Otherwise:

EnPACM, bit [7]

When FEAT_PAuth_LR is implemented:

Otherwise:

EnIDCP128, bit [6]

When FEAT_SYSREG128 is implemented:

Otherwise:

EASE, bit [5]

When FEAT_DoubleFault2 is implemented:

Otherwise:

EnANERR, bit [4]

When FEAT_ANERR is implemented:

Otherwise:

EnADERR, bit [3]

When FEAT_ADERR is implemented:

Otherwise:

NMEA, bit [2]

When FEAT_DoubleFault2 is implemented:

Otherwise:

Bits [1:0]

Accessing SCTLR2_EL1

SCTLR2_EL1: System Control Register (EL1)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:13]

CPTM0, bit [12]When FEAT_CPA2 is implemented and the Effective value of HCR_EL2.E2H is 1:

Otherwise:

CPTM, bit [11]When FEAT_CPA2 is implemented:

Otherwise:

CPTA0, bit [10]When FEAT_CPA2 is implemented and the Effective value of HCR_EL2.E2H is 1:

Otherwise:

CPTA, bit [9]When FEAT_CPA2 is implemented:

Otherwise:

EnPACM0, bit [8]When FEAT_PAuth_LR is implemented:

Otherwise:

EnPACM, bit [7]When FEAT_PAuth_LR is implemented:

Otherwise:

EnIDCP128, bit [6]When FEAT_SYSREG128 is implemented:

Otherwise:

EASE, bit [5]When FEAT_DoubleFault2 is implemented:

Otherwise:

EnANERR, bit [4]When FEAT_ANERR is implemented:

Otherwise:

EnADERR, bit [3]When FEAT_ADERR is implemented:

Otherwise:

NMEA, bit [2]When FEAT_DoubleFault2 is implemented:

Otherwise:

Bits [1:0]

Accessing SCTLR2_EL1

CPTM0, bit [12]

When FEAT_CPA2 is implemented and the Effective value of HCR_EL2.E2H is 1:

CPTM, bit [11]

When FEAT_CPA2 is implemented:

CPTA0, bit [10]

When FEAT_CPA2 is implemented and the Effective value of HCR_EL2.E2H is 1:

CPTA, bit [9]

When FEAT_CPA2 is implemented:

EnPACM0, bit [8]

When FEAT_PAuth_LR is implemented:

EnPACM, bit [7]

When FEAT_PAuth_LR is implemented:

EnIDCP128, bit [6]

When FEAT_SYSREG128 is implemented:

EASE, bit [5]

When FEAT_DoubleFault2 is implemented:

EnANERR, bit [4]

When FEAT_ANERR is implemented:

EnADERR, bit [3]

When FEAT_ADERR is implemented:

NMEA, bit [2]

When FEAT_DoubleFault2 is implemented: