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S3_<op1>_<Cn>_<Cm>_<op2>: IMPLEMENTATION DEFINED Registers

Purpose

This area of the instruction set space is reserved for IMPLEMENTATION DEFINED registers.

Configuration

Each register in this space is a 128-bit register that can also be accessed as a 64-bit value. If it is accessed as a 64-bit register, accesses read and write bits [63:0] and do not modify bits [127:64].

Attributes

S3_<op1>_<Cn>_<Cm>_<op2> is a:

Field descriptions

When FEAT_SYSREG128 is implemented:

12712612512412312212112011911811711611511411311211111010910810710610510410310210110099989796
IMPLEMENTATION DEFINED
9594939291908988878685848382818079787776757473727170696867666564
IMPLEMENTATION DEFINED
6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [127:0]

IMPLEMENTATION DEFINED.

Otherwise:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

Accessing S3_<op1>_<Cn>_<Cm>_<op2>

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, S3_<op1>_C<Cn>_C<Cm>_<op2>

op0op1CRnCRmop2
0b11op1[2:0]0b1x11Cm[3:0]op2[2:0]

if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && SCTLR_EL1.TIDCP == '1' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL2 then AArch64.ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL3 then AArch64.ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t);

MSR S3_<op1>_C<Cn>_C<Cm>_<op2>, <Xt>

op0op1CRnCRmop2
0b11op1[2:0]0b1x11Cm[3:0]op2[2:0]

if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && SCTLR_EL1.TIDCP == '1' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL2 then AArch64.ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL3 then AArch64.ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t);

When FEAT_SYSREG128 is implemented

MRRS <Xt+1>, <Xt>, S3_<op1>_C<Cn>_C<Cm>_<op2>

op0op1CRnCRmop2
0b11op1[2:0]0b1x11Cm[3:0]op2[2:0]

if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnIDCP128 == '0' then UNDEFINED; elsif !ELIsInHost(EL0) && SCTLR_EL1.TIDCP == '1' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x14); else AArch64.SystemAccessTrap(EL1, 0x14); elsif ELIsInHost(EL0) && SCTLR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif !ELIsInHost(EL0) && (!IsSCTLR2EL1Enabled() || SCTLR2_EL1.EnIDCP128 == '0') then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x14); else AArch64.SystemAccessTrap(EL1, 0x14); elsif ELIsInHost(EL0) && (!IsSCTLR2EL2Enabled() || SCTLR2_EL2.EnIDCP128 == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && !ELIsInHost(EL0) && (!IsHCRXEL2Enabled() || HCRX_EL2.EnIDCP128 == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.EnIDCP128 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else AArch64.ImpDefSysRegRead128(op0, op1, CRn, CRm, op2, t, t + 1); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnIDCP128 == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.EnIDCP128 == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.EnIDCP128 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else AArch64.ImpDefSysRegRead128(op0, op1, CRn, CRm, op2, t, t + 1); elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnIDCP128 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.EnIDCP128 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else AArch64.ImpDefSysRegRead128(op0, op1, CRn, CRm, op2, t, t + 1); elsif PSTATE.EL == EL3 then AArch64.ImpDefSysRegRead128(op0, op1, CRn, CRm, op2, t, t + 1);

When FEAT_SYSREG128 is implemented

MSRR S3_<op1>_C<Cn>_C<Cm>_<op2>, <Xt+1>, <Xt>

op0op1CRnCRmop2
0b11op1[2:0]0b1x11Cm[3:0]op2[2:0]

if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnIDCP128 == '0' then UNDEFINED; elsif !ELIsInHost(EL0) && SCTLR_EL1.TIDCP == '1' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x14); else AArch64.SystemAccessTrap(EL1, 0x14); elsif ELIsInHost(EL0) && SCTLR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif !ELIsInHost(EL0) && (!IsSCTLR2EL1Enabled() || SCTLR2_EL1.EnIDCP128 == '0') then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x14); else AArch64.SystemAccessTrap(EL1, 0x14); elsif ELIsInHost(EL0) && (!IsSCTLR2EL2Enabled() || SCTLR2_EL2.EnIDCP128 == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && !ELIsInHost(EL0) && (!IsHCRXEL2Enabled() || HCRX_EL2.EnIDCP128 == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.EnIDCP128 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else AArch64.ImpDefSysRegWrite128(op0, op1, CRn, CRm, op2, t, t + 1); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnIDCP128 == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.EnIDCP128 == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.EnIDCP128 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else AArch64.ImpDefSysRegWrite128(op0, op1, CRn, CRm, op2, t, t + 1); elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnIDCP128 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.EnIDCP128 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else AArch64.ImpDefSysRegWrite128(op0, op1, CRn, CRm, op2, t, t + 1); elsif PSTATE.EL == EL3 then AArch64.ImpDefSysRegWrite128(op0, op1, CRn, CRm, op2, t, t + 1);