Describes the Statistical Profiling implementation to software
This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMSIDR_EL1 are UNDEFINED.
PMSIDR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| ALTCLK | FPF | EFT | CRR | PBT | Format | CountSize | MaxSize | Interval | FDS | FnE | ERnd | LDS | ArchInst | FL | FT | FE | |||||||||||||||
Reserved, RES0.
Alternate clock domain.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| ALTCLK | Meaning |
|---|---|
| 0b0000 |
Alternate clock domain not implemented, or CPU clock domain. |
| 0b0001 |
SMCU clock domain. |
| 0b1111 |
IMPLEMENTATION DEFINED clock domain. |
All other values are reserved.
FEAT_SPE_ALTCLK implements the functionality identified by a nonzero value.
For example, if the PE includes an SME implementation that executes SME instructions in an external SMCU clock domain, PMSIDR_EL1.ALTCLK is 0b0001.
Access to this field is RO.
Floating-point flag.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| FPF | Meaning |
|---|---|
| 0b0 |
Operation Type packets for scalar and Advanced SIMD operations do not contain floating-point or Advanced SIMD information. |
| 0b1 |
Operation Type packets for scalar and Advanced SIMD operations contain floating-point or Advanced SIMD information. |
FEAT_SPE_FPF implements the functionality identified by the value 1.
Access to this field is RO.
Extended filtering by operation type.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EFT | Meaning |
|---|---|
| 0b0 |
PMSFCR_EL1.{SIMDm, FPm, STm, Bm, LDm, SIMD, FP} are RES0. |
| 0b1 |
PMSFCR_EL1.{SIMDm, FPm, STm, Bm, LDm, SIMD, FP} are implemented. |
FEAT_SPE_EFT implements the functionality identified by the value 1.
Access to this field is RO.
Call Return branch records.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| CRR | Meaning |
|---|---|
| 0b0 |
Operation Type packets for branches do not contain Call Return information. |
| 0b1 |
Operation Type packets for branches contain Call Return information. |
FEAT_SPE_CRR implements the functionality identified by the value 1.
Access to this field is RO.
Previous branch target Address packet.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| PBT | Meaning |
|---|---|
| 0b0 |
Previous branch target Address packet not supported. |
| 0b1 |
Previous branch target Address packet support implemented. |
FEAT_SPEv1p2 implements the OPTIONAL functionality identified by the value 1.
Access to this field is RO.
Defines the format of the sample records.
| Format | Meaning |
|---|---|
| 0b0000 |
Format 0. |
All other values are reserved.
Access to this field is RO.
Defines the size of the counters.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| CountSize | Meaning |
|---|---|
| 0b0010 |
12-bit saturating counters. |
| 0b0011 |
16-bit saturating counters. |
All other values are reserved.
Access to this field is RO.
Defines the largest size for a single record, rounded up to a power-of-two. If this is the same as the minimum alignment (PMBIDR_EL1.Align), then each record is exactly this size.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| MaxSize | Meaning |
|---|---|
| 0b0100 |
16 bytes. |
| 0b0101 |
32 bytes. |
| 0b0110 |
64 bytes. |
| 0b0111 |
128 bytes. |
| 0b1000 |
256 bytes. |
| 0b1001 |
512 bytes. |
| 0b1010 |
1KB. |
| 0b1011 |
2KB. |
All other values are reserved.
The values 0b0100 and 0b0101 are not permitted for an implementation.
Access to this field is RO.
Recommended minimum sampling interval. This provides guidance from the implementer to the smallest minimum sampling interval, N.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| Interval | Meaning |
|---|---|
| 0b0000 |
256. |
| 0b0010 |
512. |
| 0b0011 |
768. |
| 0b0100 |
1,024. |
| 0b0101 |
1,536. |
| 0b0110 |
2,048. |
| 0b0111 |
3,072. |
| 0b1000 |
4,096. |
All other values are reserved.
Access to this field is RO.
Filter by data source.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| FDS | Meaning |
|---|---|
| 0b0 |
PMSDSFR_EL1 is not implemented and PMSFCR_EL1.FDS is RES0. |
| 0b1 |
PMSDSFR_EL1 and PMSFCR_EL1.FDS are implemented. |
FEAT_SPE_FDS implements the functionality identified by the value 1.
Access to this field is RO.
Filtering by events, inverted.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| FnE | Meaning |
|---|---|
| 0b0 |
PMSNEVFR_EL1 is not implemented and PMSFCR_EL1.FnE is RES0. |
| 0b1 |
PMSNEVFR_EL1 and PMSFCR_EL1.FnE are implemented. |
FEAT_SPEv1p2 implements the functionality identified by the value 1.
Access to this field is RO.
Defines how the random number generator is used in determining the interval between samples, when enabled by PMSIRR_EL1.RND.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| ERnd | Meaning |
|---|---|
| 0b0 |
The random number is added at the start of the interval, and the sample is taken and a new interval started when the combined interval expires. |
| 0b1 |
The random number is added and the new interval started after the interval programmed in PMSIRR_EL1.INTERVAL expires, and the sample is taken when the random interval expires. |
Access to this field is RO.
Data source indicator for sampled load instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| LDS | Meaning |
|---|---|
| 0b0 |
Loaded data source not implemented. |
| 0b1 |
Loaded data source implemented. |
Access to this field is RO.
Architectural instruction profiling.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| ArchInst | Meaning |
|---|---|
| 0b0 |
Micro-op sampling implemented. |
| 0b1 |
Architecture instruction sampling implemented. |
Access to this field is RO.
Filtering by latency. This bit is RAO.
Reads as 0b1.
Access to this field is RO.
Filtering by operation type. This bit is RAO.
Reads as 0b1.
Access to this field is RO.
Filtering by events. This bit is RAO.
Reads as 0b1.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, PMSIDR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1001 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMSIDR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMSIDR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMSIDR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMSIDR_EL1;