Provides EL1 configuration options for the Performance Monitors.
This register is present only when FEAT_EBEP is implemented or FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMECR_EL1 are UNDEFINED.
PMECR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | SSE | KPME | PMEE | ||||||||||||||||||||||||||||
Reserved, RES0.
Snapshot Enable. Controls the generation of Capture events.
| SSE | Meaning |
|---|---|
| 0b00 |
Capture events are disabled. |
| 0b10 |
Capture events are enabled and prohibited. |
| 0b11 |
Capture events are enabled and allowed. |
All other values are reserved.
The reset behavior of this field is:
Reserved, RES0.
Local (Kernel) PMU Exception Enable. Enables PMU exceptions taken to the current Exception level.
| KPME | Meaning |
|---|---|
| 0b0 |
PMU exceptions taken to the current Exception level are disabled. |
| 0b1 |
PMU exceptions taken to the current Exception level are not affected by this field. |
The reset behavior of this field is:
Reserved, RES0.
Performance Monitors Exception Enable. Controls the generation of PMUIRQ signal and PMU exception at EL0 and EL1.
| PMEE | Meaning |
|---|---|
| 0b00 |
PMUIRQ signal is enabled, and PMU exception is disabled. |
| 0b10 |
PMUIRQ signal is disabled, and PMU exception is disabled. |
| 0b11 |
PMUIRQ signal is disabled, and PMU exception is enabled. |
All other values are reserved.
This field is ignored by the PE when any of the following are true:
The reset behavior of this field is:
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, PMECR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1110 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPM2 == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HDFGRTR2_EL2.nPMECR_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPM2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMECR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPM2 == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.EnPM2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMECR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMECR_EL1;
MSR PMECR_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1110 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPM2 == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3.FGTEn2 == '0') || HDFGWTR2_EL2.nPMECR_EL1 == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPM2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMECR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.EnPM2 == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.EnPM2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMECR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMECR_EL1 = X[t, 64];