Defines which Common architectural events and Common microarchitectural events are implemented, or counted, using PMU events in the ranges 0x0020 to 0x003F and 0x4020 to 0x403F.
For more information about the Common events and the use of the PMCEID<n>_EL0 registers see 'The PMU event number space and common events'.
AArch64 System register PMCEID1_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCEID1[31:0].
AArch64 System register PMCEID1_EL0 bits [63:32] are architecturally mapped to AArch32 System register PMCEID3[31:0].
AArch64 System register PMCEID1_EL0 bits [31:0] are architecturally mapped to External register PMU.PMCEID1[31:0].
AArch64 System register PMCEID1_EL0 bits [63:32] are architecturally mapped to External register PMU.PMCEID3[31:0].
This register is present only when FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMCEID1_EL0 are UNDEFINED.
PMCEID1_EL0 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IDhi31 | IDhi30 | IDhi29 | IDhi28 | IDhi27 | IDhi26 | IDhi25 | IDhi24 | IDhi23 | IDhi22 | IDhi21 | IDhi20 | IDhi19 | IDhi18 | IDhi17 | IDhi16 | IDhi15 | IDhi14 | IDhi13 | IDhi12 | IDhi11 | IDhi10 | IDhi9 | IDhi8 | IDhi7 | IDhi6 | IDhi5 | IDhi4 | IDhi3 | IDhi2 | IDhi1 | IDhi0 |
| ID31 | ID30 | ID29 | ID28 | ID27 | ID26 | ID25 | ID24 | ID23 | ID22 | ID21 | ID20 | ID19 | ID18 | ID17 | ID16 | ID15 | ID14 | ID13 | ID12 | ID11 | ID10 | ID9 | ID8 | ID7 | ID6 | ID5 | ID4 | ID3 | ID2 | ID1 | ID0 |
IDhi[n] corresponds to Common event (0x4020 + n).
For each bit:
| IDhi<n> | Meaning |
|---|---|
| 0b0 |
The Common event is not implemented, or not counted. |
| 0b1 |
The Common event is implemented. |
When the value of a bit in the field is 1, the corresponding Common event is implemented and counted.
Arm recommends that if a Common event is never counted, the value of the corresponding bit is 0.
A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional Common event.
Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n>_EL0 registers of that earlier version of the PMU architecture.
Reserved, RES0.
ID[n] corresponds to Common event (0x0020 + n).
For each bit:
| ID<n> | Meaning |
|---|---|
| 0b0 |
The Common event is not implemented, or not counted. |
| 0b1 |
The Common event is implemented. |
When the value of a bit in the field is 1, the corresponding Common event is implemented and counted.
Arm recommends that if a Common event is never counted, the value of the corresponding bit is 0.
A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional Common event.
Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n>_EL0 registers of that earlier version of the PMU architecture.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, PMCEID1_EL0
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1001 | 0b1100 | 0b111 |
if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0.UEN == '0') then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.TID == '1' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMCEIDn_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMCEID1_EL0; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMCEIDn_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMCEID1_EL0; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMCEID1_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = PMCEID1_EL0;