Stage 1 Permission Indirection Register for privileged access of the EL2 or EL2&0 translation regime.
This register is present only when FEAT_S1PIE is implemented. Otherwise, direct accesses to PIR_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
PIR_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Perm15 | Perm14 | Perm13 | Perm12 | Perm11 | Perm10 | Perm9 | Perm8 | ||||||||||||||||||||||||
| Perm7 | Perm6 | Perm5 | Perm4 | Perm3 | Perm2 | Perm1 | Perm0 | ||||||||||||||||||||||||
Represents stage 1 Base Permissions.
| Perm<m> | Meaning |
|---|---|
| 0b0000 |
No access, Overlay applied. |
| 0b0001 |
Read, Overlay applied. |
| 0b0010 |
Execute, Overlay applied. |
| 0b0011 |
Read and Execute, Overlay applied. |
| 0b0100 |
Reserved - treated as No access, Overlay applied. |
| 0b0101 |
Read and Write, Overlay applied. |
| 0b0110 |
Read, Write and Execute, Overlay applied. |
| 0b0111 |
Read, Write and Execute, Overlay applied. |
| 0b1000 |
Read, Overlay not applied. |
| 0b1001 |
Read, GCS Read and GCS Write, Overlay not applied. |
| 0b1010 |
Read and Execute, Overlay not applied. |
| 0b1011 |
Reserved - treated as No access, Overlay not applied. |
| 0b1100 |
Read and Write, Overlay not applied. |
| 0b1101 |
Reserved - treated as No access, Overlay not applied. |
| 0b1110 |
Read, Write and Execute, Overlay not applied. |
| 0b1111 |
Reserved - treated as No access, Overlay not applied. |
This field is permitted to be cached in a TLB.
When stage 1 Indirect Permission mechanism is disabled, this register is ignored.
The reset behavior of this field is:
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the register name PIR_EL2 or PIR_EL1 are not guaranteed to be ordered with respect to accesses using the other register name.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, PIR_EL2
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b1010 | 0b0010 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.PIEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.PIEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PIR_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = PIR_EL2;
MSR PIR_EL2, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b1010 | 0b0010 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.PIEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.PIEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PIR_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then PIR_EL2 = X[t, 64];
MRS <Xt>, PIR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0010 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.PIEn == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.nPIR_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.PIEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() == '111' then X[t, 64] = NVMem[0x2A0]; else X[t, 64] = PIR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.PIEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.PIEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then X[t, 64] = PIR_EL2; else X[t, 64] = PIR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PIR_EL1;
MSR PIR_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0010 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.PIEn == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.nPIR_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.PIEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() == '111' then NVMem[0x2A0] = X[t, 64]; else PIR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.PIEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.PIEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif ELIsInHost(EL2) then PIR_EL2 = X[t, 64]; else PIR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PIR_EL1 = X[t, 64];