Describes the features provided by the AArch32 Advanced SIMD and Floating-point implementation.
Must be interpreted with MVFR0_EL1 and MVFR1_EL1.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
AArch64 System register MVFR2_EL1 bits [31:0] are architecturally mapped to AArch32 System register MVFR2[31:0].
In an implementation where at least one Exception level supports execution in AArch32 state, but there is no support for Advanced SIMD and floating-point operation, this register is RAZ.
MVFR2_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | FPMisc | SIMDMisc | |||||||||||||||||||||||||||||
Reserved, RES0.
Indicates whether the floating-point implementation provides support for miscellaneous VFP features.
| FPMisc | Meaning |
|---|---|
| 0b0000 |
Not implemented, or no support for miscellaneous features. |
| 0b0001 |
Support for Floating-point selection. |
| 0b0010 |
As 0b0001, and Floating-point Conversion to Integer with Directed Rounding modes. |
| 0b0011 |
As 0b0010, and Floating-point Round to Integer Floating-point. |
| 0b0100 |
As 0b0011, and Floating-point MaxNum and MinNum. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0100.
Indicates whether the Advanced SIMD implementation provides support for miscellaneous Advanced SIMD features.
| SIMDMisc | Meaning |
|---|---|
| 0b0000 |
Not implemented, or no support for miscellaneous features. |
| 0b0001 |
Floating-point Conversion to Integer with Directed Rounding modes. |
| 0b0010 |
As 0b0001, and Floating-point Round to Integer Floating-point. |
| 0b0011 |
As 0b0010, and Floating-point MaxNum and MinNum. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000 and 0b0011.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UNKNOWN | |||||||||||||||||||||||||||||||
| UNKNOWN | |||||||||||||||||||||||||||||||
Reserved, UNKNOWN.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, MVFR2_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0011 | 0b010 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = MVFR2_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = MVFR2_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = MVFR2_EL1;