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ID_MMFR2_EL1: AArch32 Memory Model Feature Register 2

Purpose

Provides information about the implemented memory model and memory management support in AArch32 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.

Configuration

AArch64 System register ID_MMFR2_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_MMFR2[31:0].

Attributes

ID_MMFR2_EL1 is a 64-bit register.

Field descriptions

When AArch32 is supported:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
HWAccFlgWFIStallMemBarrUniTLBHvdTLBL1HvdRngL1HvdBGL1HvdFG

Bits [63:32]

Reserved, RES0.

HWAccFlg, bits [31:28]

Hardware Access Flag. In earlier versions of the Arm Architecture, this field indicates support for a Hardware Access flag, as part of the VMSAv7 implementation.

The value of this field is an IMPLEMENTATION DEFINED choice of:

HWAccFlgMeaning
0b0000

Not supported.

0b0001

Support for VMSAv7 Access flag, updated in hardware.

All other values are reserved.

From Armv8.0, 0b0001 is not permitted.

Access to this field is RO.

WFIStall, bits [27:24]

Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling.

The value of this field is an IMPLEMENTATION DEFINED choice of:

WFIStallMeaning
0b0000

Not supported.

0b0001

Support for WFI stalling.

All other values are reserved.

Access to this field is RO.

MemBarr, bits [23:20]

Memory Barrier. Indicates the supported memory barrier System instructions in the (coproc==0b1111) encoding space:

The value of this field is an IMPLEMENTATION DEFINED choice of:

MemBarrMeaning
0b0000

None supported.

0b0001

Supported memory barrier System instructions are:

  • Data Synchronization Barrier (DSB).
0b0010

As for 0b0001, and adds:

  • Instruction Synchronization Barrier (ISB).
  • Data Memory Barrier (DMB).

All other values are reserved.

From Armv8.0, the values 0b000 and 0b0001 are not permitted.

Arm deprecates the use of these operations. ID_ISAR4.Barrier_instrs indicates the level of support for the preferred barrier instructions.

Access to this field is RO.

UniTLB, bits [19:16]

Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation.

The value of this field is an IMPLEMENTATION DEFINED choice of:

UniTLBMeaning
0b0000

Not supported.

0b0001

Supported unified TLB maintenance operations are:

  • Invalidate all entries in the TLB.
  • Invalidate TLB entry by VA.
0b0010

As for 0b0001, and adds:

  • Invalidate TLB entries by ASID match.
0b0011

As for 0b0010, and adds:

  • Invalidate instruction TLB and data TLB entries by VA All ASID. This is a shared unified TLB operation.
0b0100

As for 0b0011, and adds:

  • Invalidate Hyp mode unified TLB entry by VA.
  • Invalidate entire Non-secure PL1&0 unified TLB.
  • Invalidate entire Hyp mode unified TLB.
0b0101

As for 0b0100, and adds the following operations: TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, TLBIMVALH.

0b0110

As for 0b0101, and adds the following operations: TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, TLBIIPAS2L.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0110.

Access to this field is RO.

HvdTLB, bits [15:12]

If the Unified TLB field (UniTLB, bits [19:16]) is not 0000, then the meaning of this field is IMPLEMENTATION DEFINED. Arm deprecates the use of this field by software.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

L1HvdRng, bits [11:8]

Level 1 Harvard cache Range. Indicates the supported Level 1 cache maintenance range operations, for a Harvard cache implementation.

The value of this field is an IMPLEMENTATION DEFINED choice of:

L1HvdRngMeaning
0b0000

Not supported.

0b0001

Supported Level 1 Harvard cache maintenance range operations are:

  • Invalidate data cache range by VA.
  • Invalidate instruction cache range by VA.
  • Clean data cache range by VA.
  • Clean and invalidate data cache range by VA.

All other values are reserved.

From Armv8.0, the value 0b0001 is not permitted.

Access to this field is RO.

L1HvdBG, bits [7:4]

Level 1 Harvard cache Background fetch. Indicates the supported Level 1 cache background fetch operations, for a Harvard cache implementation. When supported, background fetch operations are non-blocking operations.

The value of this field is an IMPLEMENTATION DEFINED choice of:

L1HvdBGMeaning
0b0000

Not supported.

0b0001

Supported Level 1 Harvard cache background fetch operations are:

  • Fetch instruction cache range by VA.
  • Fetch data cache range by VA.

All other values are reserved.

From Armv8.0, the value 0b0001 is not permitted.

Access to this field is RO.

L1HvdFG, bits [3:0]

Level 1 Harvard cache Foreground fetch. Indicates the supported Level 1 cache foreground fetch operations, for a Harvard cache implementation. When supported, foreground fetch operations are blocking operations.

The value of this field is an IMPLEMENTATION DEFINED choice of:

L1HvdFGMeaning
0b0000

Not supported.

0b0001

Supported Level 1 Harvard cache foreground fetch operations are:

  • Fetch instruction cache range by VA.
  • Fetch data cache range by VA.

All other values are reserved.

From Armv8.0, the value 0b0001 is not permitted.

Access to this field is RO.

Otherwise:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
UNKNOWN
UNKNOWN

Bits [63:0]

Reserved, UNKNOWN.

Accessing ID_MMFR2_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ID_MMFR2_EL1

op0op1CRnCRmop2
0b110b0000b00000b00010b110

if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_MMFR2_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_MMFR2_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_MMFR2_EL1;