Provides additional information about implemented memory model and memory management support in AArch64.
Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.
ID_AA64MMFR4_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | E3DSE | RES0 | |||||||||||||||||||||||||||||
| RES0 | E2H0 | NV_frac | FGWTE3 | HACDBS | ASID2 | EIESB | RES0 | ||||||||||||||||||||||||
Reserved, RES0.
Delegated SError exceptions from EL3. Describes support for delegated SError injection from EL3.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| E3DSE | Meaning |
|---|---|
| 0b0000 |
FEAT_E3DSE is not implemented. |
| 0b0001 | FEAT_E3DSE is implemented. The following are implemented: |
All other values are reserved.
FEAT_E3DSE implements the functionality described by the value 0b0001.
Access to this field is RO.
Reserved, RES0.
Indicates support for programming HCR_EL2.E2H.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| E2H0 | Meaning |
|---|---|
| 0b0000 |
FEAT_E2H0 is implemented. |
| 0b1110 |
FEAT_E2H0 is not implemented. HCR_EL2.NV1 is RAZ/WI. |
| 0b1111 |
FEAT_E2H0 is not implemented. |
All other values are reserved.
If FEAT_NV is not implemented, then the value 0b1110 is not permitted.
If FEAT_E2H0 is implemented and FEAT_VHE is not implemented, then HCR_EL2.E2H is RES0.
If FEAT_E2H0 is implemented and FEAT_VHE is implemented, then HCR_EL2.E2H can be programmed to 0 or 1.
If FEAT_E2H0 is not implemented then:
Access to this field is RO.
Indicates support for a subset of FEAT_NV and FEAT_NV2 behaviors.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NV_frac | Meaning |
|---|---|
| 0b0000 |
Support for FEAT_NV and FEAT_NV2 is described in ID_AA64MMFR2_EL1.NV. |
| 0b0001 | FEAT_NV and FEAT_NV2 are implemented, but all of the following apply:
|
All other values are reserved.
Access to this field is RO.
Indicates support for Fine Grained Write Trap EL3 feature.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| FGWTE3 | Meaning |
|---|---|
| 0b0000 |
Fine Grained Write Trap EL3 is not supported. |
| 0b0001 |
Fine Grained Write Trap EL3 is supported. |
All other values are reserved.
FEAT_FGWTE3 implements the functionality identified by the value 0b0001.
Access to this field is RO.
Support for Hardware accelerator for cleaning Dirty state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| HACDBS | Meaning |
|---|---|
| 0b0000 |
Hardware accelerator for cleaning Dirty state is not supported. |
| 0b0001 |
Hardware accelerator for cleaning Dirty state is supported. |
All other values are reserved.
FEAT_HACDBS implements the functionality identified by the value 0b0001.
Access to this field is RO.
Indicates support for concurrent use of two ASIDs.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| ASID2 | Meaning |
|---|---|
| 0b0000 |
FEAT_ASID2 is not implemented. |
| 0b0001 |
FEAT_ASID2 is implemented. |
All other values are reserved.
From Armv9.5, the value 0b0000 is not permitted.
Access to this field is RO.
Early Implicit Error Synchronization event. Indicates whether the implicit Error synchronization event inserted on taking an exception to ELx when SCTLR_ELx.IESB is 1 is inserted before or after the exception is taken.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EIESB | Meaning |
|---|---|
| 0b1111 |
An implicit Error synchronization event is always inserted after an exception is taken. |
| 0b0000 |
Behavior is not described. |
| 0b0001 |
When SError exceptions are routed to EL3, and either FEAT_DoubleFault is not implemented or the Effective value of SCR_EL3.NMEA is 1, an implicit Error synchronization event is inserted before an exception taken to EL3. |
| 0b0010 |
When SError exceptions are routed to ELx, and either FEAT_DoubleFault2 is not implemented or the Effective value of the applicable one of SCR_EL3.NMEA or SCTLR2_ELx.NMEA is 1, an implicit Error synchronization event is inserted before an exception taken to ELx. |
All other values are reserved.
This field describes the PE behavior on taking an exception to ELx when SCTLR_ELx.IESB is 1. This field does not apply when SCTLR_ELx.IESB is 0.
Inserting the event before the exception is taken means that if the Error synchronization event causes an SError exception to become pending, and SError exceptions are not masked and not disabled, then the SError exception is taken in place of the original exception.
Access to this field is RO.
Reserved, RES0.
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, ID_AA64MMFR4_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0111 | 0b100 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64MMFR4_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64MMFR4_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_AA64MMFR4_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_AA64MMFR4_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64MMFR4_EL1;