Invalidate all instruction caches of the PE executing the instruction to the Point of Unification.
AArch64 System instruction IC IALLU performs the same function as AArch32 System instruction ICIALLU.
IC IALLU is a 64-bit System instruction.
This instruction has no applicable fields.
The value in the register specified by <Xt> is ignored.
The Rt field should be set to 0b11111. If the Rt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:
The instruction is UNDEFINED.
The instruction behaves as if the Rt field is set to 0b11111.
Accesses to this instruction use the following encodings in the System instruction encoding space:
IC IALLU{, <Xt>}
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b000 | 0b0111 | 0b0101 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TPU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TOCU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.ICIALLU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.FB == '1' then AArch64.IC(CacheOpScope_ALLUIS); else AArch64.IC(CacheOpScope_ALLU); elsif PSTATE.EL == EL2 then AArch64.IC(CacheOpScope_ALLU); elsif PSTATE.EL == EL3 then AArch64.IC(CacheOpScope_ALLU);