Provides controls for traps of MSRR, MSR and MCR writes of System registers.
This register is present only when FEAT_FGT2 is implemented. Otherwise, direct accesses to HFGWTR2_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
HFGWTR2_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | nRCWSMASK_EL1 | RES0 | nPFAR_EL1 | ||||||||||||||||||||||||||||
Reserved, RES0.
Trap MSR or MSRR writes of RCWSMASK_EL1 at EL1 using AArch64 to EL2.
| nRCWSMASK_EL1 | Meaning |
|---|---|
| 0b0 |
If EL2 is implemented and enabled in the current Security state, then MSR or MSRR writes of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18 for 64-bit access and 0x14 for 128-bit access, unless the write generates a higher priority exception. |
| 0b1 |
MSR or MSRR writes of RCWSMASK_EL1 are not trapped by this mechanism. |
This field is ignored by the PE and treated as zero when all of the following are true:
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of PFAR_EL1 at EL1 using AArch64 to EL2.
| nPFAR_EL1 | Meaning |
|---|---|
| 0b0 |
If EL2 is implemented and enabled in the current Security state, then MSR writes of PFAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
| 0b1 |
MSR writes of PFAR_EL1 are not trapped by this mechanism. |
This field is ignored by the PE and treated as zero when all of the following are true:
The reset behavior of this field is:
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, HFGWTR2_EL2
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0011 | 0b0001 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = NVMem[0x2C8]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FGTEn2 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = HFGWTR2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HFGWTR2_EL2;
MSR HFGWTR2_EL2, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0011 | 0b0001 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem[0x2C8] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FGTEn2 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HFGWTR2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HFGWTR2_EL2 = X[t, 64];