Allows producer to update write index for HDBSS.
This register is present only when FEAT_HDBSS is implemented. Otherwise, direct accesses to HDBSSPROD_EL2 are UNDEFINED.
HDBSSPROD_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| FSC | RES0 | INDEX | |||||||||||||||||||||||||||||
Reserved, RES0.
Fault Status Code.
| FSC | Meaning | Applies when |
|---|---|---|
| 0b000000 |
The PE has not experienced any error on writes to the HDBSS. | |
| 0b010000 |
External Abort on write to HDBSS. | |
| 0b101000 |
Granule Protection Fault on write to HDBSS. | When FEAT_RME is implemented |
If this field is non-zero then one or more HDBSS writes have experienced a fault since this field was last set to zero, and the associated HDBSS entries have been lost.
All other values are reserved.
The reset behavior of this field is:
Reserved, RES0.
This field indicates the index of the HDBSS entry that will be written to next.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, HDBSSPROD_EL2
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0010 | 0b0011 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = NVMem[0x300]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.HDBSSEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.HDBSSEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = HDBSSPROD_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HDBSSPROD_EL2;
MSR HDBSSPROD_EL2, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0010 | 0b0011 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem[0x300] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.HDBSSEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.HDBSSEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HDBSSPROD_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HDBSSPROD_EL2 = X[t, 64];