Control register for HACDBS structure.
This register is present only when FEAT_HACDBS is implemented. Otherwise, direct accesses to HACDBSBR_EL2 are UNDEFINED.
HACDBSBR_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | BADDR | ||||||||||||||||||||||||||||||
| BADDR | EN | RES0 | SZ | ||||||||||||||||||||||||||||
Reserved, RES0.
HACDBS base address, bits [55:12].
Bits of this field above the implemented physical address size, indicated in ID_AA64MMFR0_EL1.PARange, are RES0.
Similarly, based on the value of the SZ field of this register, for encodings of the SZ field greater than 4KB, bits [(SZ+12-1):12] of this field are RES0. HACDBS must be aligned to its size.
The reset behavior of this field is:
Enable use of HACDBS.
| EN | Meaning |
|---|---|
| 0b0 |
Hardware accelerator for cleaning Dirty state is disabled. |
| 0b1 |
Hardware accelerator for cleaning Dirty state is enabled. |
If SCR_EL3.HACDBSEn is set to 0, then this field behaves as 0 for all purposes other than a direct read of the value of this bit.
The reset behavior of this field is:
Reserved, RES0.
Size of the HACDBS.
| SZ | Meaning |
|---|---|
| 0b0001 |
8KB |
| 0b0010 |
16KB |
| 0b0011 |
32KB |
| 0b0100 |
64KB |
| 0b0101 |
128KB |
| 0b0110 |
256KB |
| 0b0111 |
512KB |
| 0b1000 |
1MB |
| 0b1001 |
2MB |
All other values are reserved.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, HACDBSBR_EL2
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0010 | 0b0011 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = NVMem[0x2F0]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.HACDBSEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.HACDBSEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = HACDBSBR_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HACDBSBR_EL2;
MSR HACDBSBR_EL2, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0010 | 0b0011 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem[0x2F0] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.HACDBSEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.HACDBSEn == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HACDBSBR_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HACDBSBR_EL2 = X[t, 64];