The control register for Granule Protection Table base address.
This register is present only when FEAT_RME is implemented. Otherwise, direct accesses to GPTBR_EL3 are UNDEFINED.
GPTBR_EL3 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | BADDR | ||||||||||||||||||||||||||||||
| BADDR | |||||||||||||||||||||||||||||||
Reserved, RES0.
Base address for the level 0 GPT.
This field represents bits [51:12] of the level 0 GPT base address.
The level 0 GPT is aligned in memory to the greater of:
Bits [x:0] of the base address are treated as zero, where:
| GPCCR_EL3.PPS | pps |
|---|---|
| 0b000 | 32 |
| 0b001 | 36 |
| 0b010 | 40 |
| 0b011 | 42 |
| 0b100 | 44 |
| 0b101 | 48 |
| 0b110 | 52 |
| GPCCR_EL3.L0GPTSZ | l0gptsz |
|---|---|
| 0b0000 | 30 |
| 0b0100 | 34 |
| 0b0110 | 36 |
| 0b1001 | 39 |
If x is greater than 11, then BADDR[x - 12:0] are RES0.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, GPTBR_EL3
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b110 | 0b0010 | 0b0001 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = GPTBR_EL3;
MSR GPTBR_EL3, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b110 | 0b0010 | 0b0001 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3.GPTBR_EL3 == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else GPTBR_EL3 = X[t, 64];