Controls behaviors of the FP8 instructions.
This register is present only when FEAT_FPMR is implemented. Otherwise, direct accesses to FPMR are UNDEFINED.
A direct or indirect read of this register occurs in program order relative to a direct write of this register without explicit synchronization.
FPMR is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | LSCALE2 | ||||||||||||||||||||||||||||||
| NSCALE | RES0 | LSCALE | OSC | OSM | RES0 | F8D | F8S2 | F8S1 | |||||||||||||||||||||||
Reserved, RES0.
Downscaling value for instructions that convert the second FP8 input data stream to other floating-point formats.
This value is an unsigned integer that is subtracted from the result exponent.
The reset behavior of this field is:
Scaling value for instructions that convert other floating-point formats to an FP8 format.
This value is a signed integer that is added to the operand exponent.
The reset behavior of this field is:
Reserved, RES0.
Downscaling value.
This value is an unsigned integer that is subtracted from:
The product or the sum-of-products exponent, for multiplication instructions with FP8 operands.
The result exponent, for instructions that convert the first FP8 input data stream to other floating-point formats.
The reset behavior of this field is:
Overflow saturation for FP8 convert instructions. Specifies the result when a floating-point Overflow exception is detected.
| OSC | Meaning |
|---|---|
| 0b0 |
Infinity or NaN is generated. |
| 0b1 |
Maximum normal number is generated. |
The reset behavior of this field is:
Overflow saturation for FP8 multiplication instructions. Specifies the result when a floating-point Overflow exception is detected.
| OSM | Meaning |
|---|---|
| 0b0 |
Infinity is generated. |
| 0b1 |
Maximum normal number is generated. |
The reset behavior of this field is:
Reserved, RES0.
Destination result format for instructions that convert other floating-point values to an FP8 format.
| F8D | Meaning |
|---|---|
| 0b000 |
Arm FP8 E5M2 format. |
| 0b001 |
Arm FP8 E4M3 format. |
All other values are reserved.
Reserved values identify an unsupported format.
The reset behavior of this field is:
Second FP8 input data stream format for multiplication instructions with FP8 operands, and the corresponding instructions that convert an FP8 format to other floating-point formats.
| F8S2 | Meaning |
|---|---|
| 0b000 |
Arm FP8 E5M2 format. |
| 0b001 |
Arm FP8 E4M3 format. |
All other values are reserved.
Reserved values identify an unsupported format.
The reset behavior of this field is:
First FP8 input data stream format for multiplication instructions with FP8 operands, and the corresponding instructions that convert an FP8 format to a other floating-point formats.
| F8S1 | Meaning |
|---|---|
| 0b000 |
Arm FP8 E5M2 format. |
| 0b001 |
Arm FP8 E4M3 format. |
All other values are reserved.
Reserved values identify an unsupported format.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, FPMR
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b0100 | 0b0100 | 0b010 |
if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnFPM == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TFP == '1' then UNDEFINED; elsif !ELIsInHost(EL0) && SCTLR_EL1.EnFPM == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2.EnFPM == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && SCR_EL3.HXEn == '0') || HCRX_EL2.EnFPM == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.EnFPM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELIsInHost(EL0) && CPACR_EL1.FPEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x00); else AArch64.SystemAccessTrap(EL1, 0x07); elsif ELIsInHost(EL0) && CPTR_EL2.FPEN != '11' then AArch64.SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else X[t, 64] = FPMR; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnFPM == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TFP == '1' then UNDEFINED; elsif EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && SCR_EL3.HXEn == '0') || HCRX_EL2.EnFPM == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.EnFPM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif CPACR_EL1.FPEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else X[t, 64] = FPMR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnFPM == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TFP == '1' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.EnFPM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELIsInHost(EL2) && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else X[t, 64] = FPMR; elsif PSTATE.EL == EL3 then if CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else X[t, 64] = FPMR;
MSR FPMR, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b0100 | 0b0100 | 0b010 |
if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnFPM == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TFP == '1' then UNDEFINED; elsif !ELIsInHost(EL0) && SCTLR_EL1.EnFPM == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2.EnFPM == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && SCR_EL3.HXEn == '0') || HCRX_EL2.EnFPM == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.EnFPM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELIsInHost(EL0) && CPACR_EL1.FPEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x00); else AArch64.SystemAccessTrap(EL1, 0x07); elsif ELIsInHost(EL0) && CPTR_EL2.FPEN != '11' then AArch64.SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else FPMR = X[t, 64]; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnFPM == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TFP == '1' then UNDEFINED; elsif EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && SCR_EL3.HXEn == '0') || HCRX_EL2.EnFPM == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.EnFPM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif CPACR_EL1.FPEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else FPMR = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.EnFPM == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TFP == '1' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.EnFPM == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !ELIsInHost(EL2) && CPTR_EL2.TFP == '1' then AArch64.SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2.FPEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3.TFP == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x07); else FPMR = X[t, 64]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TFP == '1' then AArch64.SystemAccessTrap(EL3, 0x07); else FPMR = X[t, 64];