Records that an SError exception has been consumed by an ESB instruction.
AArch64 System register DISR_EL1 bits [31:0] are architecturally mapped to AArch32 System register DISR[31:0].
This register is present only when FEAT_RAS is implemented. Otherwise, direct accesses to DISR_EL1 are UNDEFINED.
DISR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| A | RES0 | IDS | RES0 | WU | RES0 | AET | EA | RES0 | WnRV | WnR | DFSC | ||||||||||||||||||||
Reserved, RES0.
Set to 1 when an ESB instruction defers an asynchronous SError exception. If the implementation does not include any sources of SError exception that can be synchronized by an Error Synchronization Barrier, then this bit is RES0.
The reset behavior of this field is:
Reserved, RES0.
Indicates the deferred SError exception type.
| IDS | Meaning |
|---|---|
| 0b0 |
Deferred error uses architecturally-defined format. |
The reset behavior of this field is:
Reserved, RES0.
Write update. See the description of ESR_ELx.WU for an SError exception.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Asynchronous Error Type. See the description of ESR_ELx.AET for an SError exception.
The reset behavior of this field is:
External abort Type. See the description of ESR_ELx.EA for an SError exception.
The reset behavior of this field is:
Reserved, RES0.
Write-not-Read Valid. See the description of ESR_ELx.WnRV for an SError exception.
The reset behavior of this field is:
Reserved, RES0.
Write-not-Read. See the description of ESR_ELx.WnR for an SError exception.
The reset behavior of this field is:
Reserved, RES0.
Fault Status Code. See the description of ESR_ELx.DFSC for an SError exception.
The reset behavior of this field is:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| A | RES0 | IDS | ISS | ||||||||||||||||||||||||||||
Reserved, RES0.
Set to 1 when an ESB instruction defers an asynchronous SError exception. If the implementation does not include any sources of SError exception that can be synchronized by an Error Synchronization Barrier, then this bit is RES0.
The reset behavior of this field is:
Reserved, RES0.
Indicates the deferred SError exception type.
| IDS | Meaning |
|---|---|
| 0b1 |
Deferred error uses IMPLEMENTATION DEFINED format. |
The reset behavior of this field is:
IMPLEMENTATION DEFINED syndrome. See the description of ESR_ELx[23:0] for an SError exception.
The reset behavior of this field is:
An indirect write to DISR_EL1 made by an ESB instruction does not require an explicit synchronization operation for the value that is written to be observed by a direct read of DISR_EL1 occurring in program order after the ESB instruction.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, DISR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1100 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2.AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2.TMEA == '1')) then X[t, 64] = VDISR_EL2; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && SCR_EL3.EnDSE == '1' then X[t, 64] = VDISR_EL3; elsif HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then X[t, 64] = Zeros(64); else X[t, 64] = DISR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && SCR_EL3.EnDSE == '1' then X[t, 64] = VDISR_EL3; elsif HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then X[t, 64] = Zeros(64); else X[t, 64] = DISR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = DISR_EL1;
MSR DISR_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1100 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2.AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2.TMEA == '1')) then VDISR_EL2 = X[t, 64]; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && SCR_EL3.EnDSE == '1' then VDISR_EL3 = X[t, 64]; elsif HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then return; else DISR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_E3DSE) && SCR_EL3.EnDSE == '1' then VDISR_EL3 = X[t, 64]; elsif HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then return; else DISR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then DISR_EL1 = X[t, 64];