Clean data cache by address to Point of Coherency.
AArch64 System instruction DC CVAC performs the same function as AArch32 System instruction DCCMVAC.
DC CVAC is a 64-bit System instruction.
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Virtual address to use. No alignment restrictions apply to this VA.
If EL0 access is enabled, when executed at EL0, the instruction may generate a Permission fault, subject to the constraints described in 'MMU faults generated by cache maintenance operations'.
Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'The data cache maintenance instruction (DC)'.
Accesses to this instruction use the following encodings in the System instruction encoding space:
DC CVAC, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b011 | 0b0111 | 0b1010 | 0b001 |
if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && SCTLR_EL1.UCI == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && HCR_EL2.TPCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCCVAC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2.UCI == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.DC(X[t, 64], CacheType_Data, CacheOp_Clean, CacheOpScope_PoC); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TPCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCCVAC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.DC(X[t, 64], CacheType_Data, CacheOp_Clean, CacheOpScope_PoC); elsif PSTATE.EL == EL2 then AArch64.DC(X[t, 64], CacheType_Data, CacheOp_Clean, CacheOpScope_PoC); elsif PSTATE.EL == EL3 then AArch64.DC(X[t, 64], CacheType_Data, CacheOp_Clean, CacheOpScope_PoC);