Provides information about the architecture of the caches.
AArch64 System register CTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register CTR[31:0].
CTR_EL0 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | TminLine | ||||||||||||||||||||||||||||||
| RES1 | RES0 | DIC | IDC | CWG | ERG | DminLine | L1Ip | RES0 | IminLine | ||||||||||||||||||||||
Reserved, RES0.
Tag minimum Line. Log2 of the number of words covered by Allocation Tags in the smallest cache line of all caches which can contain Allocation tags that are controlled by the PE.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Instruction cache invalidation requirements for data to instruction coherence.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| DIC | Meaning |
|---|---|
| 0b0 |
Instruction cache invalidation to the Point of Unification is required for data to instruction coherence. |
| 0b1 |
Instruction cache invalidation to the Point of Unification is not required for data to instruction coherence. |
All PEs in the same Inner Shareable shareability domain must have a common value of this field.
Access to this field is RO.
Data cache clean requirements for instruction to data coherence. The meaning of this bit is:
The value of this field is an IMPLEMENTATION DEFINED choice of:
| IDC | Meaning |
|---|---|
| 0b0 |
Data cache clean to the Point of Unification is required for instruction to data coherence, unless CLIDR_EL1.LoC == 0b000 or (CLIDR_EL1.LoUIS == 0b000 and CLIDR_EL1.LoUU == 0b000). |
| 0b1 |
Data cache clean to the Point of Unification is not required for instruction to data coherence. |
If CTR_EL0.DIC is 1 then the value reported in this field must also be 1.
The Effective value of IDC is 1 if any of the following are true:
All PEs in the same Inner Shareable shareability domain must have a common Effective value of IDC.
Access to this field is RO.
Cache writeback granule. Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified.
A value of 0b0000 indicates that this register does not provide Cache writeback granule information and either:
Values greater than 0b1001 are reserved.
Arm recommends that an implementation that does not support cache write-back implements this field as 0b0001. This applies, for example, to an implementation that supports only write-through caches.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Exclusives reservation granule, and, if FEAT_TME is implemented, transactional reservation granule. Log2 of the number of words of the maximum size of the reservation granule for the Load-Exclusive and Store-Exclusive instructions, and, if FEAT_TME is implemented, for detecting transactional conflicts.
A value of 0b0000 indicates that this register does not provide granule information and the architectural maximum of 512 words (2KB) must be assumed.
Value 0b0001 and values greater than 0b1001 are reserved.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Level 1 instruction cache policy. Indicates the indexing and tagging policy for the L1 instruction cache.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| L1Ip | Meaning |
|---|---|
| 0b00 |
Reserved. |
| 0b01 |
ASID-tagged Virtual Index, Virtual Tag (AIVIVT). |
| 0b10 |
Virtual Index, Physical Tag (VIPT). |
| 0b11 |
Physical Index, Physical Tag (PIPT). |
From Armv8.0, the value 0b01 is reserved.
Access to this field is RO.
Reserved, RES0.
Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, CTR_EL0
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b0000 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && SCTLR_EL1.UCT == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && HCR_EL2.TID2 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.CTR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2.UCT == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = CTR_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID2 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.CTR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = CTR_EL0; elsif PSTATE.EL == EL2 then X[t, 64] = CTR_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = CTR_EL0;