Control register for the virtual timer.
AArch64 System register CNTV_CTL_EL0 bits [31:0] are architecturally mapped to AArch32 System register CNTV_CTL[31:0].
CNTV_CTL_EL0 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | ISTATUS | IMASK | ENABLE | ||||||||||||||||||||||||||||
Reserved, RES0.
The status of the timer. This bit indicates whether the timer condition is met:
| ISTATUS | Meaning |
|---|---|
| 0b0 |
Timer condition is not met. |
| 0b1 |
Timer condition is met. |
When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted.
When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.
The reset behavior of this field is:
Access to this field is RO.
Timer interrupt mask bit. Permitted values are:
| IMASK | Meaning |
|---|---|
| 0b0 |
Timer interrupt is not masked by the IMASK bit. |
| 0b1 |
Timer interrupt is masked by the IMASK bit. |
For more information, see the description of the ISTATUS bit.
The reset behavior of this field is:
Enables the timer. Permitted values are:
| ENABLE | Meaning |
|---|---|
| 0b0 |
Timer disabled. |
| 0b1 |
Timer enabled. |
Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTV_TVAL_EL0 continues to count down.
Disabling the output signal might be a power-saving option.
The reset behavior of this field is:
When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic CNTV_CTL_EL0 or CNTV_CTL_EL02 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, CNTV_CTL_EL0
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1110 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1.EL0VTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0VTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && SCR_EL3.NS == '0' && IsFeatureImplemented(FEAT_SEL2) then X[t, 64] = CNTHVS_CTL_EL2; elsif ELIsInHost(EL0) && SCR_EL3.NS == '1' then X[t, 64] = CNTHV_CTL_EL2; else X[t, 64] = CNTV_CTL_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() == '111' then X[t, 64] = NVMem[0x170]; else X[t, 64] = CNTV_CTL_EL0; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && SCR_EL3.NS == '0' && IsFeatureImplemented(FEAT_SEL2) then X[t, 64] = CNTHVS_CTL_EL2; elsif ELIsInHost(EL2) && SCR_EL3.NS == '1' then X[t, 64] = CNTHV_CTL_EL2; else X[t, 64] = CNTV_CTL_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = CNTV_CTL_EL0;
MSR CNTV_CTL_EL0, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1110 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1.EL0VTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0VTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && SCR_EL3.NS == '0' && IsFeatureImplemented(FEAT_SEL2) then CNTHVS_CTL_EL2 = X[t, 64]; elsif ELIsInHost(EL0) && SCR_EL3.NS == '1' then CNTHV_CTL_EL2 = X[t, 64]; else CNTV_CTL_EL0 = X[t, 64]; elsif PSTATE.EL == EL1 then if EL2Enabled() && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EffectiveHCR_EL2_NVx() == '111' then NVMem[0x170] = X[t, 64]; else CNTV_CTL_EL0 = X[t, 64]; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) && SCR_EL3.NS == '0' && IsFeatureImplemented(FEAT_SEL2) then CNTHVS_CTL_EL2 = X[t, 64]; elsif ELIsInHost(EL2) && SCR_EL3.NS == '1' then CNTHV_CTL_EL2 = X[t, 64]; else CNTV_CTL_EL0 = X[t, 64]; elsif PSTATE.EL == EL3 then CNTV_CTL_EL0 = X[t, 64];
MRS <Xt>, CNTV_CTL_EL02
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b101 | 0b1110 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then if EL2Enabled() && !ELIsInHost(EL0) && CNTHCTL_EL2.EL1NVVCT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = NVMem[0x170]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then X[t, 64] = CNTV_CTL_EL0; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X[t, 64] = CNTV_CTL_EL0; else UNDEFINED;
MSR CNTV_CTL_EL02, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b101 | 0b1110 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then if EL2Enabled() && !ELIsInHost(EL0) && CNTHCTL_EL2.EL1NVVCT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else NVMem[0x170] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then CNTV_CTL_EL0 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then CNTV_CTL_EL0 = X[t, 64]; else UNDEFINED;