CNTFRQ_EL0 | Jon's Arm Reference

This register is provided so that software can discover the frequency of the system counter. It must be programmed with this value as part of system initialization. The value of the register is not interpreted by hardware.

Configuration

AArch64 System register CNTFRQ_EL0 bits [31:0] are architecturally mapped to AArch32 System register CNTFRQ[31:0].

Attributes

Field descriptions

Bits [63:32]

Bits [31:0]

Clock frequency. Indicates the system counter clock frequency, in Hz.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing CNTFRQ_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, CNTFRQ_EL0

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b0000	0b000

if PSTATE.EL == EL0 then if !ELIsInHost(EL0) && CNTKCTL_EL1.<EL0PCTEN,EL0VCTEN> == '00' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif ELIsInHost(EL0) && CNTHCTL_EL2.<EL0PCTEN,EL0VCTEN> == '00' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = CNTFRQ_EL0; elsif PSTATE.EL == EL1 then X[t, 64] = CNTFRQ_EL0; elsif PSTATE.EL == EL2 then X[t, 64] = CNTFRQ_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = CNTFRQ_EL0;

MSR CNTFRQ_EL0, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b0000	0b000

if IsHighestEL(PSTATE.EL) then CNTFRQ_EL0 = X[t, 64]; else UNDEFINED;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
Clock frequency