Functional controls for the Branch Record Buffer.
This register is present only when FEAT_BRBE is implemented. Otherwise, direct accesses to BRBFCR_EL1 are UNDEFINED.
BRBFCR_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | BANK | RES0 | CONDDIR | DIRCALL | INDCALL | RTN | INDIRECT | DIRECT | EnI | RES0 | PAUSED | LASTFAILED | RES0 | ||||||||||||||||||
Reserved, RES0.
Branch record buffer bank access control.
| BANK | Meaning |
|---|---|
| 0b00 |
Select branch records 0 to 31. |
| 0b01 |
Select branch records 32 to 63. |
All other values are reserved.
The reset behavior of this field is:
Reserved, RES0.
Match on conditional direct branch instructions.
| CONDDIR | Meaning |
|---|---|
| 0b0 |
Do not match on conditional direct branch instructions. |
| 0b1 |
Match on conditional direct branch instructions. |
The reset behavior of this field is:
Match on direct branch with link instructions.
| DIRCALL | Meaning |
|---|---|
| 0b0 |
Do not match on direct branch with link instructions. |
| 0b1 |
Match on direct branch with link instructions. |
The reset behavior of this field is:
Match on indirect branch with link instructions.
| INDCALL | Meaning |
|---|---|
| 0b0 |
Do not match on indirect branch with link instructions. |
| 0b1 |
Match on indirect branch with link instructions. |
The reset behavior of this field is:
Match on function return instructions.
| RTN | Meaning |
|---|---|
| 0b0 |
Do not match on function return instructions. |
| 0b1 |
Match on function return instructions. |
The reset behavior of this field is:
Match on indirect branch instructions.
| INDIRECT | Meaning |
|---|---|
| 0b0 |
Do not match on indirect branch instructions. |
| 0b1 |
Match on indirect branch instructions. |
The reset behavior of this field is:
Match on unconditional direct branch instructions.
| DIRECT | Meaning |
|---|---|
| 0b0 |
Do not match on unconditional direct branch instructions. |
| 0b1 |
Match on unconditional direct branch instructions. |
The reset behavior of this field is:
Include or exclude matches.
| EnI | Meaning |
|---|---|
| 0b0 |
Include records for matches, and exclude records for non-matches. |
| 0b1 |
Exclude records for matches, and include records for non-matches. |
The reset behavior of this field is:
Reserved, RES0.
Branch recording Paused status.
| PAUSED | Meaning |
|---|---|
| 0b0 |
Branch recording is not Paused. |
| 0b1 |
Branch recording is Paused. |
The reset behavior of this field is:
Indicates transaction failure or cancellation.
| LASTFAILED | Meaning |
|---|---|
| 0b0 |
Indicates that no transactions in a non-prohibited region have failed or been canceled since the last Branch record was generated. |
| 0b1 |
Indicates that at least one transaction in a non-prohibited region has failed or been canceled since the last Branch record was generated. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, BRBFCR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b001 | 0b1001 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.nBRBCTL == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = BRBFCR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = BRBFCR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = BRBFCR_EL1;
MSR BRBFCR_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b001 | 0b1001 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.nBRBCTL == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else BRBFCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.SBRBE != '11' && SCR_EL3.NS == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.SBRBE == 'x0' && SCR_EL3.NS == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else BRBFCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then BRBFCR_EL1 = X[t, 64];