Performs stage 1 address translation from EL0, with permissions as if reading from the given virtual address from EL0, using the following translation regime:
When FEAT_RME is implemented, if the Effective value of SCR_EL3.{NSE, NS} is a reserved value, this instruction is UNDEFINED at EL3.
There are no configuration notes.
AT S1E0R is a 64-bit System instruction.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Input address for translation | |||||||||||||||||||||||||||||||
| Input address for translation | |||||||||||||||||||||||||||||||
Input address for translation. The resulting address can be read from the PAR_EL1.
If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.
Accesses to this instruction use the following encodings in the System instruction encoding space:
AT S1E0R, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b000 | 0b0111 | 0b1000 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.AT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.ATS1E0R == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.AT(X[t, 64], TranslationStage_1, EL0, ATAccess_Read); elsif PSTATE.EL == EL2 then AArch64.AT(X[t, 64], TranslationStage_1, EL0, ATAccess_Read); elsif PSTATE.EL == EL3 then AArch64.AT(X[t, 64], TranslationStage_1, EL0, ATAccess_Read);