Provides information on the events that an architected activity monitor event counter AMEVCNTR0<n>_EL0 counts.
AArch64 System register AMEVTYPER0<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register AMEVTYPER0<n>[31:0].
AArch64 System register AMEVTYPER0<n>_EL0 bits [31:0] are architecturally mapped to External register AMU.AMEVTYPER0<n>[31:0].
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMEVTYPER0<n>_EL0 are UNDEFINED.
AMEVTYPER0<n>_EL0 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | evtCount | ||||||||||||||||||||||||||||||
Reserved, RES0.
Event to count. The event number of the event that is counted by the architected activity monitor event counter AMEVCNTR0<n>_EL0. The value of this field is architecturally mandated for each architected counter.
The following table shows the mapping between required event numbers and the corresponding counters:
The value of this field is an IMPLEMENTATION DEFINED choice of:
| evtCount | Meaning | Applies when |
|---|---|---|
| 0x0011 |
Processor frequency cycles | When n == 0 |
| 0x4004 |
Constant frequency cycles | When n == 1 |
| 0x0008 |
Instructions retired | When n == 2 |
| 0x4005 |
Memory stall cycles | When n == 3 |
Access to this field is RO.
If <n> is greater than or equal to the number of architected activity monitor event counters, reads and writes of AMEVTYPER0<n>_EL0 are UNDEFINED.
AMCGCR_EL0.CG0NC identifies the number of architected activity monitor event counters.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, AMEVTYPER0<m>_EL0 ; Where m = 0-3
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b011 | 0b1101 | 0b011:m[3] | m[2:0] |
integer m = UInt(CRm<0>:op2<2:0>); if m >= 4 then UNDEFINED; elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TAM == '1' then UNDEFINED; elsif AMUSERENR_EL0.EN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = AMEVTYPER0_EL0[m]; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TAM == '1' then UNDEFINED; elsif EL2Enabled() && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = AMEVTYPER0_EL0[m]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TAM == '1' then UNDEFINED; elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = AMEVTYPER0_EL0[m]; elsif PSTATE.EL == EL3 then X[t, 64] = AMEVTYPER0_EL0[m];