Controls the top level mapping of the TEX[0], C, and B memory region attributes.
This register is banked between PRRR and PRRR_S and PRRR_NS.
AArch32 System register PRRR bits [31:0] are architecturally mapped to AArch64 System register MAIR_EL1[31:0] when EL3 is not implemented or EL3 is using AArch64.
AArch32 System register PRRR bits [31:0] are architecturally mapped to AArch32 System register MAIR0[31:0] when EL3 is not implemented or EL3 is using AArch64.
AArch32 System register PRRR bits [31:0] (PRRR_S) are architecturally mapped to AArch32 System register MAIR0[31:0] (MAIR0_S) when EL3 is using AArch32.
AArch32 System register PRRR bits [31:0] (PRRR_NS) are architecturally mapped to AArch32 System register MAIR0[31:0] (MAIR0_NS) when EL3 is using AArch32.
This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to PRRR are UNDEFINED.
MAIR0 and PRRR are the same register, with a different view depending on the value of TTBCR.EAE:
PRRR is a 32-bit register.
This register has the following instances:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NOS7 | NOS6 | NOS5 | NOS4 | NOS3 | NOS2 | NOS1 | NOS0 | RES0 | NS1 | NS0 | DS1 | DS0 | TR7 | TR6 | TR5 | TR4 | TR3 | TR2 | TR1 | TR0 | |||||||||||
Not Outer Shareable. NOS<n> is the Outer Shareable property for memory attributes n, if the region is mapped as Normal memory that is not Inner Non-cacheable, Outer Non-cacheable, and the appropriate PRRR.{NS0, NS1} field identifies the region as shareable. n is the value of the concatenation of the {TEX[0], C, B} bits from the Translation table descriptor. The possible values of each NOS<n> field other than NOS6 are:
| NOS<n> | Meaning |
|---|---|
| 0b0 |
Memory region is Outer Shareable. |
| 0b1 |
Memory region is Inner Shareable. |
The value of this bit is ignored if the region is:
The meaning of the NOS6 field is IMPLEMENTATION DEFINED.
The reset behavior of this field is:
Reserved, RES0.
Mapping of S = 1 attribute for Normal memory regions. This field is used in determining the Shareability of a memory region that is mapped to Normal memory and both:
| NS1 | Meaning |
|---|---|
| 0b0 |
Region is Non-shareable. |
| 0b1 |
Region is shareable. The value of the appropriate PRRR.NOS<n> field determines whether the region is Inner Shareable or Outer Shareable. |
The reset behavior of this field is:
Mapping of S = 0 attribute for Normal memory regions. This field is used in determining the Shareability of a memory region that is mapped to Normal memory and both:
| NS0 | Meaning |
|---|---|
| 0b0 |
Region is Non-shareable. |
| 0b1 |
Region is shareable. The value of the appropriate PRRR.NOS<n> field determines whether the region is Inner Shareable or Outer Shareable. |
The reset behavior of this field is:
Mapping of S = 1 attribute for Device memory. From Armv8.0, all types of Device memory are Outer Shareable, and therefore this bit is RES1.
The reset behavior of this field is:
Mapping of S = 0 attribute for Device memory. From Armv8.0, all types of Device memory are Outer Shareable, and therefore this bit is RES1.
The reset behavior of this field is:
TR<n> is the primary TEX mapping for memory attributes n, and defines the mapped memory type for a region with attributes n. n is the value of the concatenation of the {TEX[0], C, B} bits from the Translation table descriptor. The possible values for each field other than TR6 are:
| TR<n> | Meaning |
|---|---|
| 0b00 |
Device-nGnRnE memory |
| 0b01 |
Device-nGnRE memory |
| 0b10 |
Normal memory |
The value 0b11 is reserved. The effect of programming a field to 0b11 is CONSTRAINED UNPREDICTABLE.
The meaning of the TR6 field is IMPLEMENTATION DEFINED.
When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1010 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then R[t] = MAIR0_NS; else R[t] = PRRR_NS; else if TTBCR.EAE == '1' then R[t] = MAIR0; else R[t] = PRRR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then R[t] = MAIR0_NS; else R[t] = PRRR_NS; else if TTBCR.EAE == '1' then R[t] = MAIR0; else R[t] = PRRR; elsif PSTATE.EL == EL3 then if TTBCR.EAE == '1' then if SCR.NS == '0' then R[t] = MAIR0_S; else R[t] = MAIR0_NS; else if SCR.NS == '0' then R[t] = PRRR_S; else R[t] = PRRR_NS;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1010 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then MAIR0_NS = R[t]; else PRRR_NS = R[t]; else if TTBCR.EAE == '1' then MAIR0 = R[t]; else PRRR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then MAIR0_NS = R[t]; else PRRR_NS = R[t]; else if TTBCR.EAE == '1' then MAIR0 = R[t]; else PRRR = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' && CP15SDISABLE == Signal_High then UNDEFINED; elsif SCR.NS == '0' && CP15SDISABLE2 == Signal_High then UNDEFINED; else if TTBCR.EAE == '1' then if SCR.NS == '0' then MAIR0_S = R[t]; else MAIR0_NS = R[t]; else if SCR.NS == '0' then PRRR_S = R[t]; else PRRR_NS = R[t];