When EL3 is implemented and can use AArch32, holds the vector base address for any exception that is taken to Monitor mode.
Secure software must program the MVBAR with the required initial value as part of the PE boot sequence.
This register is present only when EL3 is capable of using AArch32. Otherwise, direct accesses to MVBAR are UNDEFINED.
It is IMPLEMENTATION DEFINED whether MVBAR[0] has a fixed value and ignored writes, or takes the last value written to it.
On a Warm reset into EL3 using AArch32, the reset value of MVBAR is an IMPLEMENTATION DEFINED choice between the following:
MVBAR is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VBA | Reserved | ||||||||||||||||||||||||||||||
Vector Base Address. Bits[31:5] of the base address of the exception vectors for exceptions taken to this Exception level. Bits[4:0] of an exception vector are the exception offset.
Reserved, see Configurations.
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if IsHighestEL(EL1) then R[t] = RVBAR; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif !ELUsingAArch32(EL2) && SCR_EL3.<NS,EEL2> == '01' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if IsHighestEL(EL2) then R[t] = RVBAR; else UNDEFINED; elsif PSTATE.EL == EL3 then R[t] = MVBAR;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif !ELUsingAArch32(EL2) && SCR_EL3.<NS,EEL2> == '01' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if CP15SDISABLE == Signal_High then UNDEFINED; elsif CP15SDISABLE2 == Signal_High then UNDEFINED; else MVBAR = R[t];