Shows the pending status of the IRQ and FIQ interrupts and the SError exceptions.
AArch32 System register ISR bits [31:0] are architecturally mapped to AArch64 System register ISR_EL1[31:0].
This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ISR are UNDEFINED.
ISR is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | A | I | F | RES0 | |||||||||||||||||||||||||||
Reserved, RES0.
SError exception pending bit:
| A | Meaning |
|---|---|
| 0b0 |
No pending SError exception. |
| 0b1 |
An SError exception is pending. |
If all of the following apply then this field shows the pending status of virtual SError exceptions:
Otherwise, this field shows the pending status of physical SError exceptions.
If the SError exception is edge-triggered, this field is cleared to zero when the physical SError exception is taken.
IRQ pending bit. Indicates whether an IRQ interrupt is pending:
| I | Meaning |
|---|---|
| 0b0 |
No pending IRQ. |
| 0b1 |
An IRQ interrupt is pending. |
If all of the following apply then this field shows the pending status of virtual IRQ interrupts:
Otherwise, this field shows the pending status of physical IRQ interrupts.
FIQ pending bit. Indicates whether an FIQ interrupt is pending.
| F | Meaning |
|---|---|
| 0b0 |
No pending FIQ. |
| 0b1 |
An FIQ interrupt is pending. |
If all of the following apply then this field shows the pending status of virtual FIQ interrupts:
Otherwise, this field shows the pending status of physical FIQ interrupts.
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else R[t] = ISR; elsif PSTATE.EL == EL2 then R[t] = ISR; elsif PSTATE.EL == EL3 then R[t] = ISR;