Gives information about the AArch32 programmers' model.
Must be interpreted with ID_PFR0 and ID_PFR1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
AArch32 System register ID_PFR2 bits [31:0] are architecturally mapped to AArch64 System register ID_PFR2_EL1[31:0].
This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_PFR2 are UNDEFINED.
ID_PFR2 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | RAS_frac | SSBS | CSV3 | ||||||||||||||||||||||||||||
Reserved, RES0.
RAS Extension fractional field.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| RAS_frac | Meaning |
|---|---|
| 0b0000 |
If ID_PFR0.RAS == 0b0001, RAS Extension implemented. |
| 0b0001 | If ID_PFR0.RAS == 0b0001, as 0b0000 and adds support for additional ERXMISC<m> System registers. Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp Extension. |
All other values are reserved.
This field is valid only if ID_PFR0.RAS == 0b0001.
Access to this field is RO.
Speculative Store Bypassing controls in AArch64 state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SSBS | Meaning |
|---|---|
| 0b0000 |
AArch32 provides no mechanism to control the use of Speculative Store Bypassing. |
| 0b0001 |
AArch32 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. |
In Armv8.0, the permitted values are 0b0000 and 0b0001.
From Armv8.5, the only permitted value is 0b0001.
All other values are reserved.
Access to this field is RO.
Speculative use of faulting data.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| CSV3 | Meaning |
|---|---|
| 0b0000 |
This PE does not disclose whether data loaded under speculation with a permission or domain fault can be used to form an address or generate condition codes or SVE predicate values to be used by other instructions in the speculative sequence. |
| 0b0001 |
Data loaded under speculation with a permission or domain fault cannot be used to form an address, generate condition codes, or generate SVE predicate values to be used by other instructions in the speculative sequence. The execution timing of any other instructions in the speculative sequence is not a function of the data loaded under speculation. |
All other values are reserved.
FEAT_CSV3 implements the functionality identified by the value 0b0001.
In Armv8.0, the permitted values are 0b0000 and 0b0001.
From Armv8.5, the only permitted value is 0b0001.
If FEAT_E0PD is implemented, FEAT_CSV3 must be implemented.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0000 | 0b0011 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else R[t] = ID_PFR2; elsif PSTATE.EL == EL2 then R[t] = ID_PFR2; elsif PSTATE.EL == EL3 then R[t] = ID_PFR2;