Invalidate all instruction caches in the Inner Shareable domain of the PE executing the instruction to the Point of Unification. If branch predictors are architecturally visible, also flush branch predictors.
AArch32 System instruction ICIALLUIS performs the same function as AArch64 System instruction IC IALLUIS.
This instruction is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ICIALLUIS are UNDEFINED.
ICIALLUIS is a 32-bit System instruction.
This instruction has no applicable fields.
The value in the register specified by <Rt> is ignored.
The PE ignores the value of <Rt>. Software does not have to write a value to this register before issuing this instruction.
Accesses to this instruction use the following encodings in the System instruction encoding space:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0111 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TPU == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TICAB == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TPU == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR2.TICAB == '1' then AArch32.TakeHypTrapException(0x03); else AArch32.IC(CacheOpScope_ALLUIS); elsif PSTATE.EL == EL2 then AArch32.IC(CacheOpScope_ALLUIS); elsif PSTATE.EL == EL3 then AArch32.IC(CacheOpScope_ALLUIS);