When taking an exception to Hyp mode, holds the address to return to.
AArch32 System register ELR_hyp bits [31:0] are architecturally mapped to AArch64 System register ELR_EL2[31:0].
This register is present only when AArch32 is supported. Otherwise, direct accesses to ELR_hyp are UNDEFINED.
ELR_hyp is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Return address | |||||||||||||||||||||||||||||||
Return address.
The reset behavior of this field is:
ELR_hyp is accessible only at Hyp mode and Monitor mode.
Accesses to this register use the following encodings in the System register encoding space:
MRS{<c>}{<q>} <Rd>, ELR_hyp
| R | M | M1 |
|---|---|---|
| 0b0 | 0b1 | 0b1110 |
MSR{<c>}{<q>} ELR_hyp, <Rn>
| R | M | M1 |
|---|---|---|
| 0b0 | 0b1 | 0b1110 |