Holds the saved process state for Debug state. On entering Debug state, PSTATE information is written to this register. On exiting Debug state, values are copied from this register to PSTATE.
AArch32 System register DSPSR2 bits [31:0] are architecturally mapped to AArch64 System register DSPSR_EL0[63:32].
This register is present only when FEAT_Debugv8p9 is implemented. Otherwise, direct accesses to DSPSR2 are UNDEFINED.
DSPSR2 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | PPEND | RES0 | |||||||||||||||||||||||||||||
Reserved, RES0.
PMU exception pending. Set to the value of PSTATE.PPEND on entering Debug state, and copied to PSTATE.PPEND on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b011 | 0b0100 | 0b0101 | 0b010 |
if !Halted() then UNDEFINED; else R[t] = DSPSR2;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b011 | 0b0100 | 0b0101 | 0b010 |
if !Halted() then UNDEFINED; else DSPSR2 = R[t];