Clean data or unified cache line by set/way.
AArch32 System instruction DCCSW performs the same function as AArch64 System instruction DC CSW.
This instruction is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to DCCSW are UNDEFINED.
DCCSW is a 32-bit System instruction.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SetWay | Level | RES0 | |||||||||||||||||||||||||||||
Contains two fields:
Bits[L-1:4] are RES0.
A = Log2(ASSOCIATIVITY), L = Log2(LINELEN), B = (L + S), S = Log2(NSETS).
ASSOCIATIVITY, LINELEN (line length, in bytes), and NSETS (number of sets) have their usual meanings and are the values for the cache level being operated on. The values of A and S are rounded up to the next integer.
Cache level to operate on, minus 1. For example, this field is 0 for operations on L1 cache, or 1 for operations on L2 cache.
Reserved, RES0.
If this instruction is executed with a set, way or level argument that is larger than the value supported by the implementation then the behavior is CONSTRAINED UNPREDICTABLE and one of the following occurs:
Accesses to this instruction use the following encodings in the System instruction encoding space:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0111 | 0b1010 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TSW == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TSW == '1' then AArch32.TakeHypTrapException(0x03); else AArch32.DC(R[t], CacheOp_Clean, CacheOpScope_SetWay); elsif PSTATE.EL == EL2 then AArch32.DC(R[t], CacheOp_Clean, CacheOpScope_SetWay); elsif PSTATE.EL == EL3 then AArch32.DC(R[t], CacheOp_Clean, CacheOpScope_SetWay);