Control register for the EL1 physical timer.
This register is banked between CNTP_CTL and CNTP_CTL_S and CNTP_CTL_NS.
AArch32 System register CNTP_CTL bits [31:0] are architecturally mapped to AArch64 System register CNTP_CTL_EL0[31:0].
This register is present only when AArch32 is supported. Otherwise, direct accesses to CNTP_CTL are UNDEFINED.
CNTP_CTL is a 32-bit register.
This register has the following instances:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | ISTATUS | IMASK | ENABLE | ||||||||||||||||||||||||||||
Reserved, RES0.
The status of the timer. This bit indicates whether the timer condition is met:
| ISTATUS | Meaning |
|---|---|
| 0b0 |
Timer condition is not met. |
| 0b1 |
Timer condition is met. |
When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted.
When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.
The reset behavior of this field is:
Access to this field is RO.
Timer interrupt mask bit. Permitted values are:
| IMASK | Meaning |
|---|---|
| 0b0 |
Timer interrupt is not masked by the IMASK bit. |
| 0b1 |
Timer interrupt is masked by the IMASK bit. |
For more information, see the description of the ISTATUS bit.
The reset behavior of this field is:
Enables the timer. Permitted values are:
| ENABLE | Meaning |
|---|---|
| 0b0 |
Timer disabled. |
| 0b1 |
Timer enabled. |
Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTP_TVAL continues to count down.
Disabling the output signal might be a power-saving option.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1110 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && CNTKCTL.PL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x03); elsif ELIsInHost(EL0) && SCR_EL3.NS == '0' && IsFeatureImplemented(FEAT_SEL2) then R[t] = CNTHPS_CTL_EL2<31:0>; elsif ELIsInHost(EL0) && SCR_EL3.NS == '1' then R[t] = CNTHP_CTL_EL2<31:0>; else R[t] = CNTP_CTL; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then R[t] = CNTP_CTL_NS; else R[t] = CNTP_CTL; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then R[t] = CNTP_CTL_NS; else R[t] = CNTP_CTL; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then R[t] = CNTP_CTL_S; else R[t] = CNTP_CTL_NS;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1110 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && CNTKCTL.PL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x03); elsif ELIsInHost(EL0) && SCR_EL3.NS == '0' && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CTL_EL2 = R[t]; elsif ELIsInHost(EL0) && SCR_EL3.NS == '1' then CNTHP_CTL_EL2 = R[t]; else CNTP_CTL = R[t]; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then CNTP_CTL_NS = R[t]; else CNTP_CTL = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then CNTP_CTL_NS = R[t]; else CNTP_CTL = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then CNTP_CTL_S = R[t]; else CNTP_CTL_NS = R[t];