Invalidate all entries from branch predictors.
This instruction is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to BPIALL are UNDEFINED.
In an implementation where the branch predictors are architecturally invisible, this instruction can execute as a NOP.
BPIALL is a 32-bit System instruction.
This instruction has no applicable fields.
The value in the register specified by <Rt> is ignored.
The PE ignores the value of <Rt>. Software does not have to write a value to this register before issuing this instruction.
When HCR.FB is 1, at Non-secure EL1 this instruction executes as a BPIALLIS.
Accesses to this instruction use the following encodings in the System instruction encoding space:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0111 | 0b0101 | 0b110 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.FB == '1' then BPIALLIS(); else BPIALL(); elsif PSTATE.EL == EL2 then BPIALL(); elsif PSTATE.EL == EL3 then BPIALL();