Performs a stage 1 address translation at PL1 and in the current Security state, where the value of PSTATE.PAN determines if a write to the location will generate a Permission fault for a privileged access.
This instruction is present only when EL1 is capable of using AArch32 and FEAT_PAN2 is implemented. Otherwise, direct accesses to ATS1CPWP are UNDEFINED.
ATS1CPWP is a 32-bit System instruction.
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| IA | |||||||||||||||||||||||||||||||
Input address for translation. The resulting address can be read from the PAR.
This System instruction takes a VA as input. If EL2 is implemented and enabled in the current Security state, the resulting address is the IPA that is the output address of the stage 1 translation. Otherwise, the resulting address is a PA.
Accesses to this instruction use the following encodings in the System instruction encoding space:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0111 | 0b1001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); else AArch32.AT(R[t], TranslationStage_1, EL1, ATAccess_WritePAN); elsif PSTATE.EL == EL2 then AArch32.AT(R[t], TranslationStage_1, EL1, ATAccess_WritePAN); elsif PSTATE.EL == EL3 then if SCR.NS == '0' then AArch32.AT(R[t], TranslationStage_1, EL3, ATAccess_WritePAN); else AArch32.AT(R[t], TranslationStage_1, EL1, ATAccess_WritePAN);