Performs stage 1 address translation as defined for PL1 and the current Security state, with permissions as if reading from the given virtual address.
This instruction is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ATS1CPR are UNDEFINED.
ATS1CPR is a 32-bit System instruction.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IA | |||||||||||||||||||||||||||||||
Input address for translation. The resulting address can be read from the PAR.
This System instruction takes a VA as input. If EL2 is implemented and enabled in the current Security state, the resulting address is the IPA that is the output address of the stage 1 translation. Otherwise, the resulting address is a PA.
Accesses to this instruction use the following encodings in the System instruction encoding space:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0111 | 0b1000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); else AArch32.AT(R[t], TranslationStage_1, EL1, ATAccess_Read); elsif PSTATE.EL == EL2 then AArch32.AT(R[t], TranslationStage_1, EL1, ATAccess_Read); elsif PSTATE.EL == EL3 then if SCR.NS == '0' then AArch32.AT(R[t], TranslationStage_1, EL3, ATAccess_Read); else AArch32.AT(R[t], TranslationStage_1, EL1, ATAccess_Read);