Address Translate Stages 1 and 2 Non-secure Only Unprivileged Write
Performs stage 1 and 2 address translations as defined for PL0 and the Non-secure state, with permissions as if writing to the given virtual address.
This instruction is present only when FEAT_AA32EL2 is implemented. Otherwise, direct accesses to ATS12NSOUW are UNDEFINED.
ATS12NSOUW is a 32-bit System instruction.
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Input address for translation. The resulting address can be read from the PAR.
This System instruction takes a VA as input. The resulting address is the PA that is the output address of the stage 2 translation.
Accesses to this instruction use the following encodings in the System instruction encoding space:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b000, CRn = 0b0111, CRm = 0b1000, opc2 = 0b111)
if !IsFeatureImplemented(FEAT_AA32EL2) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsCurrentSecurityState(SS_Secure) then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && IsCurrentSecurityState(SS_Secure) then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then AArch32.AT(R[t], TranslationStage_12, EL0, ATAccess_Write); elsif PSTATE.EL == EL3 then AArch32.AT(R[t], TranslationStage_12, EL0, ATAccess_Write);
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