Provides access to the architected activity monitor event counters.
AArch32 System register AMEVCNTR0<n> bits [63:0] are architecturally mapped to AArch64 System register AMEVCNTR0<n>_EL0[63:0].
AArch32 System register AMEVCNTR0<n> bits [63:0] are architecturally mapped to External register AMU.AMEVCNTR0<n>[63:0].
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMEVCNTR0<n> are UNDEFINED.
AMEVCNTR0<n> is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACNT | |||||||||||||||||||||||||||||||
| ACNT | |||||||||||||||||||||||||||||||
Architected activity monitor event counter n.
Value of architected activity monitor event counter n, where n is the number of this register and is a number from 0 to 3.
If FEAT_AMUv1p1 is implemented, HCR_EL2.AMVOFFEN is 1, SCR_EL3.AMVOFFEN is 1, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and EL2 is using AArch64 and is implemented in the current Security state, access to these registers at EL0 or EL1 return (PCount<63:0> - AMEVCNTVOFF0<n>_EL2<63:0>).
PCount is the physical count returned when AMEVCNTR0<n> is read from EL2 or EL3.
If the counter is enabled, writes to this register have UNPREDICTABLE results.
The reset behavior of this field is:
If <n> is greater than or equal to the number of architected activity monitor event counters, reads and writes of AMEVCNTR0<n> are UNDEFINED.
AMCGCR.CG0NC identifies the number of architected activity monitor event counters.
Accesses to this register use the following encodings in the System register encoding space:
MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm> ; Where m = 0-3
| coproc | CRm | opc1 |
|---|---|---|
| 0b1111 | 0b000:m[3] | 0b0:m[2:0] |
integer m = UInt(CRm<0>:opc1<2:0>); if m >= 4 then UNDEFINED; elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then UNDEFINED; elsif !ELUsingAArch32(EL1) && AMUSERENR_EL0.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); else AArch64.AArch32SystemAccessTrap(EL1, 0x04); elsif ELUsingAArch32(EL1) && AMUSERENR.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL0) && m < 8 && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && m < 8 && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x04); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then AArch32.TakeHypTrapException(0x04); elsif EL2Enabled() && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HAFGRTR_EL2.AMEVCNTR0<m>_EL0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x04); else (R[t2], R[t]) = (AMEVCNTR0[m]<63:32>, AMEVCNTR0[m]<31:0>); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && m < 8 && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && m < 8 && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x04); elsif EL2Enabled() && !ELUsingAArch32(EL2) && CPTR_EL2.TAM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCPTR.TAM == '1' then AArch32.TakeHypTrapException(0x04); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x04); else (R[t2], R[t]) = (AMEVCNTR0[m]<63:32>, AMEVCNTR0[m]<31:0>); elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x04); else (R[t2], R[t]) = (AMEVCNTR0[m]<63:32>, AMEVCNTR0[m]<31:0>); elsif PSTATE.EL == EL3 then (R[t2], R[t]) = (AMEVCNTR0[m]<63:32>, AMEVCNTR0[m]<31:0>);
MCRR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm> ; Where m = 0-3
| coproc | CRm | opc1 |
|---|---|---|
| 0b1111 | 0b000:m[3] | 0b0:m[2:0] |
integer m = UInt(CRm<0>:opc1<2:0>); if m >= 4 then UNDEFINED; elsif PSTATE.EL == EL1 && EL2Enabled() && !ELUsingAArch32(EL2) && m < 8 && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif PSTATE.EL == EL1 && EL2Enabled() && ELUsingAArch32(EL2) && m < 8 && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x04); elsif IsHighestEL(PSTATE.EL) then AMEVCNTR0[m] = R[t2]:R[t]; else UNDEFINED;